62256.vo

EPM1270和ram62256的verilog接口程序

defparam \addr_in[2]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_12
maxii_io \addr_in[1]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [1]),
	.padio(addr_in[1]));
// synopsys translate_off
defparam \addr_in[1]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_30
maxii_io \addr_in[0]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [0]),
	.padio(addr_in[0]));
// synopsys translate_off
defparam \addr_in[0]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N3
maxii_lcell \Add0~222_I (
// Equation(s):
// \Add0~222  = !\addr[0]~reg0 
// \Add0~223  = CARRY(\addr[0]~reg0 )
// \Add0~223COUT1_253  = CARRY(\addr[0]~reg0 )

	.clk(gnd),
	.dataa(vcc),
	.datab(\addr[0]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0~222 ),
	.regout(),
	.cout(),
	.cout0(\Add0~223 ),
	.cout1(\Add0~223COUT1_253 ));
// synopsys translate_off
defparam \Add0~222_I .lut_mask = "33CC";
defparam \Add0~222_I .operation_mode = "arithmetic";
defparam \Add0~222_I .output_mode = "comb_only";
defparam \Add0~222_I .register_cascade_mode = "off";
defparam \Add0~222_I .sum_lutc_input = "datac";
defparam \Add0~222_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X6_Y3_N0
maxii_lcell \addr[7]~1361_I (
// Equation(s):
// \addr[7]~1361  = write & \Equal0~131  # !write & !\Equal1~195  & (\Equal0~131  # \addr[9]~1360 )

	.clk(gnd),
	.dataa(write),
	.datab(\Equal0~131 ),
	.datac(\addr[9]~1360 ),
	.datad(\Equal1~195 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\addr[7]~1361 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[7]~1361_I .lut_mask = "88DC";
defparam \addr[7]~1361_I .operation_mode = "normal";
defparam \addr[7]~1361_I .output_mode = "comb_only";
defparam \addr[7]~1361_I .register_cascade_mode = "off";
defparam \addr[7]~1361_I .sum_lutc_input = "datac";
defparam \addr[7]~1361_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X3_Y3_N0
maxii_lcell \addr[0]~reg0_I (
// Equation(s):
// \addr[0]~reg0  = DFFEAS(!\addr[7]~1363  & (\addr[7]~1361  & (\Add0~222 ) # !\addr[7]~1361  & \addr_in~combout [0]), GLOBAL(\clk~combout ), VCC, , \addr[7]~1367 , , , , )

	.clk(\clk~combout ),
	.dataa(\addr_in~combout [0]),
	.datab(\addr[7]~1363 ),
	.datac(\Add0~222 ),
	.datad(\addr[7]~1361 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\addr[7]~1367 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\addr[0]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[0]~reg0_I .lut_mask = "3022";
defparam \addr[0]~reg0_I .operation_mode = "normal";
defparam \addr[0]~reg0_I .output_mode = "reg_only";
defparam \addr[0]~reg0_I .register_cascade_mode = "off";
defparam \addr[0]~reg0_I .sum_lutc_input = "datac";
defparam \addr[0]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X4_Y2_N4
maxii_lcell \Add0~224_I (
// Equation(s):
// \Add0~224  = \addr[1]~reg0  $ \Add0~223 
// \Add0~225  = CARRY(!\Add0~223COUT1_253  # !\addr[1]~reg0 )

	.clk(gnd),
	.dataa(vcc),
	.datab(\addr[1]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(\Add0~223 ),
	.cin1(\Add0~223COUT1_253 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0~224 ),
	.regout(),
	.cout(\Add0~225 ),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Add0~224_I .cin0_used = "true";
defparam \Add0~224_I .cin1_used = "true";
defparam \Add0~224_I .lut_mask = "3C3F";
defparam \Add0~224_I .operation_mode = "arithmetic";
defparam \Add0~224_I .output_mode = "comb_only";
defparam \Add0~224_I .register_cascade_mode = "off";
defparam \Add0~224_I .sum_lutc_input = "cin";
defparam \Add0~224_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X4_Y2_N1
maxii_lcell \addr[1]~reg0_I (
// Equation(s):
// \addr[1]~reg0  = DFFEAS(!\addr[7]~1363  & (\addr[7]~1361  & (\Add0~224 ) # !\addr[7]~1361  & \addr_in~combout [1]), GLOBAL(\clk~combout ), VCC, , \addr[7]~1367 , , , , )

	.clk(\clk~combout ),
	.dataa(\addr_in~combout [1]),
	.datab(\Add0~224 ),
	.datac(\addr[7]~1361 ),
	.datad(\addr[7]~1363 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\addr[7]~1367 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\addr[1]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[1]~reg0_I .lut_mask = "00CA";
defparam \addr[1]~reg0_I .operation_mode = "normal";
defparam \addr[1]~reg0_I .output_mode = "reg_only";
defparam \addr[1]~reg0_I .register_cascade_mode = "off";
defparam \addr[1]~reg0_I .sum_lutc_input = "datac";
defparam \addr[1]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X4_Y2_N5
maxii_lcell \Add0~226_I (
// Equation(s):
// \Add0~226  = \addr[2]~reg0  $ (!\Add0~225 )
// \Add0~227  = CARRY(\addr[2]~reg0  & (!\Add0~225 ))
// \Add0~227COUT1_254  = CARRY(\addr[2]~reg0  & (!\Add0~225 ))

	.clk(gnd),
	.dataa(\addr[2]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\Add0~225 ),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0~226 ),
	.regout(),
	.cout(),
	.cout0(\Add0~227 ),
	.cout1(\Add0~227COUT1_254 ));
// synopsys translate_off
defparam \Add0~226_I .cin_used = "true";
defparam \Add0~226_I .lut_mask = "A50A";
defparam \Add0~226_I .operation_mode = "arithmetic";
defparam \Add0~226_I .output_mode = "comb_only";
defparam \Add0~226_I .register_cascade_mode = "off";
defparam \Add0~226_I .sum_lutc_input = "cin";
defparam \Add0~226_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X3_Y3_N5
maxii_lcell \addr[2]~reg0_I (
// Equation(s):
// \addr[2]~reg0  = DFFEAS(!\addr[7]~1363  & (\addr[7]~1361  & (\Add0~226 ) # !\addr[7]~1361  & \addr_in~combout [2]), GLOBAL(\clk~combout ), VCC, , \addr[7]~1367 , , , , )

	.clk(\clk~combout ),
	.dataa(\addr_in~combout [2]),
	.datab(\Add0~226 ),
	.datac(\addr[7]~1363 ),
	.datad(\addr[7]~1361 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\addr[7]~1367 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\addr[2]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[2]~reg0_I .lut_mask = "0C0A";
defparam \addr[2]~reg0_I .operation_mode = "normal";
defparam \addr[2]~reg0_I .output_mode = "reg_only";
defparam \addr[2]~reg0_I .register_cascade_mode = "off";
defparam \addr[2]~reg0_I .sum_lutc_input = "datac";
defparam \addr[2]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_42
maxii_io \addr_in[3]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [3]),
	.padio(addr_in[3]));
// synopsys translate_off
defparam \addr_in[3]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N6
maxii_lcell \Add0~228_I (
// Equation(s):
// \Add0~228  = \addr[3]~reg0  $ (!\Add0~225  & \Add0~227 ) # (\Add0~225  & \Add0~227COUT1_254 )
// \Add0~229  = CARRY(!\Add0~227  # !\addr[3]~reg0 )
// \Add0~229COUT1_255  = CARRY(!\Add0~227COUT1_254  # !\addr[3]~reg0 )

	.clk(gnd),
	.dataa(vcc),
	.datab(\addr[3]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\Add0~225 ),
	.cin0(\Add0~227 ),
	.cin1(\Add0~227COUT1_254 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0~228 ),
	.regout(),
	.cout(),
	.cout0(\Add0~229 ),
	.cout1(\Add0~229COUT1_255 ));
// synopsys translate_off
defparam \Add0~228_I .cin0_used = "true";
defparam \Add0~228_I .cin1_used = "true";
defparam \Add0~228_I .cin_used = "true";
defparam \Add0~228_I .lut_mask = "3C3F";
defparam \Add0~228_I .operation_mode = "arithmetic";
defparam \Add0~228_I .output_mode = "comb_only";
defparam \Add0~228_I .register_cascade_mode = "off";
defparam \Add0~228_I .sum_lutc_input = "cin";
defparam \Add0~228_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X4_Y3_N8
maxii_lcell \addr[3]~reg0_I (
// Equation(s):
// \addr[3]~reg0  = DFFEAS(!\addr[7]~1363  & (\addr[7]~1361  & (\Add0~228 ) # !\addr[7]~1361  & \addr_in~combout [3]), GLOBAL(\clk~combout ), VCC, , \addr[7]~1367 , , , , )

	.clk(\clk~combout ),
	.dataa(\addr_in~combout [3]),
	.datab(\addr[7]~1361 ),
	.datac(\Add0~228 ),
	.datad(\addr[7]~1363 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\addr[7]~1367 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\addr[3]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[3]~reg0_I .lut_mask = "00E2";
defparam \addr[3]~reg0_I .operation_mode = "normal";
defparam \addr[3]~reg0_I .output_mode = "reg_only";
defparam \addr[3]~reg0_I .register_cascade_mode = "off";
defparam \addr[3]~reg0_I .sum_lutc_input = "datac";
defparam \addr[3]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X6_Y3_N2
maxii_lcell \Equal0~129_I (
// Equation(s):
// \Equal0~129  = \addr[0]~reg0  # \addr[3]~reg0  # \addr[1]~reg0  # !\addr[2]~reg0 

	.clk(gnd),
	.dataa(\addr[2]~reg0 ),
	.datab(\addr[0]~reg0 ),
	.datac(\addr[3]~reg0 ),
	.datad(\addr[1]~reg0 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Equal0~129 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \Equal0~129_I .lut_mask = "FFFD";
defparam \Equal0~129_I .operation_mode = "normal";
defparam \Equal0~129_I .output_mode = "comb_only";
defparam \Equal0~129_I .register_cascade_mode = "off";
defparam \Equal0~129_I .sum_lutc_input = "datac";
defparam \Equal0~129_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_66
maxii_io \addr_in[5]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [5]),
	.padio(addr_in[5]));
// synopsys translate_off
defparam \addr_in[5]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_37
maxii_io \addr_in[4]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [4]),
	.padio(addr_in[4]));
// synopsys translate_off
defparam \addr_in[4]~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X4_Y2_N7
maxii_lcell \Add0~230_I (
// Equation(s):
// \Add0~230  = \addr[4]~reg0  $ !(!\Add0~225  & \Add0~229 ) # (\Add0~225  & \Add0~229COUT1_255 )
// \Add0~231  = CARRY(\addr[4]~reg0  & !\Add0~229 )
// \Add0~231COUT1_256  = CARRY(\addr[4]~reg0  & !\Add0~229COUT1_255 )

	.clk(gnd),
	.dataa(vcc),
	.datab(\addr[4]~reg0 ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(\Add0~225 ),
	.cin0(\Add0~229 ),
	.cin1(\Add0~229COUT1_255 ),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\Add0~230 ),
	.regout(),
	.cout(),
	.cout0(\Add0~231 ),
	.cout1(\Add0~231COUT1_256 ));
// synopsys translate_off
defparam \Add0~230_I .cin0_used = "true";
defparam \Add0~230_I .cin1_used = "true";
defparam \Add0~230_I .cin_used = "true";
defparam \Add0~230_I .lut_mask = "C30C";
defparam \Add0~230_I .operation_mode = "arithmetic";
defparam \Add0~230_I .output_mode = "comb_only";
defparam \Add0~230_I .register_cascade_mode = "off";
defparam \Add0~230_I .sum_lutc_input = "cin";
defparam \Add0~230_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X4_Y2_N0
maxii_lcell \addr[4]~reg0_I (
// Equation(s):
// \addr[4]~reg0  = DFFEAS(!\addr[7]~1363  & (\addr[7]~1361  & (\Add0~230 ) # !\addr[7]~1361  & \addr_in~combout [4]), GLOBAL(\clk~combout ), VCC, , \addr[7]~1367 , , , , )

	.clk(\clk~combout ),
	.dataa(\addr_in~combout [4]),
	.datab(\Add0~230 ),
	.datac(\addr[7]~1361 ),
	.datad(\addr[7]~1363 ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(\addr[7]~1367 ),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\addr[4]~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[4]~reg0_I .lut_mask = "00CA";
defparam \addr[4]~reg0_I .operation_mode = "normal";
defparam \addr[4]~reg0_I .output_mode = "reg_only";
defparam \addr[4]~reg0_I .register_cascade_mode = "off";
defparam \addr[4]~reg0_I .sum_lutc_input = "datac";
defparam \addr[4]~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X4_Y2_N8
maxii_lcell \Add0~232_I (
// Equation(s):
// \Add0~232  = \addr[5]~reg0  $ ((!\Add0~225  & \Add0~231 ) # (\Add0~225  & \Add0~231COUT1_256 ))
// \Add0~233  = CARRY(!\Add0~231  # !\addr[5]~reg0 )
// \Add0~233COUT1_257  = CARRY(!\Add0~231COUT1_256  # !\addr[5]~reg0 )

	.clk(gnd),
	.dataa(\addr[5]~reg0 ),
	.datab(vcc),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),