62256.vo

EPM1270和ram62256的verilog接口程序

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.

// VENDOR "Altera"
// PROGRAM "Quartus II"
// VERSION "Version 6.0 Build 178 04/27/2006 SJ Full Version"

// DATE "07/29/2007 20:13:31"

// 
// Device: Altera EPM240T100C5 Package TQFP100
// 

// 
// This Verilog file should be used for ModelSim (Verilog) only
// 

`timescale 1 ps/ 1 ps

module inter62256 (
	clk,
	rst,
	CS,
	OE,
	WE,
	addr,
	data_io,
	addr_in,
	read_en,
	write_en,
	write_clk,
	data_in,
	data_out,
	req,
	mode);
input 	clk;
input 	rst;
output 	CS;
output 	OE;
output 	WE;
output 	[14:0] addr;
inout 	[7:0] data_io;
input 	[7:0] addr_in;
input 	read_en;
input 	write_en;
input 	write_clk;
input 	[7:0] data_in;
output 	[7:0] data_out;
output 	req;
input 	mode;

wire gnd = 1'b0;
wire vcc = 1'b1;

tri1 devclrn;
tri1 devpor;
tri0 devoe;
// synopsys translate_off
initial $sdf_annotate("62256_v.sdo");
// synopsys translate_on

wire \data_io[0]~7 ;
wire \data_io[1]~6 ;
wire \data_io[2]~5 ;
wire \data_io[3]~4 ;
wire \data_io[4]~3 ;
wire \data_io[5]~2 ;
wire \data_io[6]~1 ;
wire \data_io[7]~0 ;
wire \clk~combout ;
wire \rst~combout ;
wire \CS~reg0 ;
wire \mode~combout ;
wire \read_en~combout ;
wire read_en0;
wire read_en1;
wire \addr[9]~1360 ;
wire \write_en~combout ;
wire write_en0;
wire write_en1;
wire \always0~0 ;
wire \Add0~237 ;
wire \Add0~237COUT1_258 ;
wire \Add0~238 ;
wire \addr[7]~1362 ;
wire \addr[9]~1375 ;
wire \addr[9]~1376 ;
wire \data_in_temp[0]~274 ;
wire \addr[7]~1365 ;
wire \addr[7]~1366 ;
wire \OE~187 ;
wire \addr[7]~1367 ;
wire \addr[8]~reg0 ;
wire \Add0~222 ;
wire \addr[7]~1361 ;
wire \addr[0]~reg0 ;
wire \Add0~223 ;
wire \Add0~223COUT1_253 ;
wire \Add0~224 ;
wire \addr[1]~reg0 ;
wire \Add0~225 ;
wire \Add0~226 ;
wire \addr[2]~reg0 ;
wire \Add0~227 ;
wire \Add0~227COUT1_254 ;
wire \Add0~228 ;
wire \addr[3]~reg0 ;
wire \Equal0~129 ;
wire \Add0~229 ;
wire \Add0~229COUT1_255 ;
wire \Add0~230 ;
wire \addr[4]~reg0 ;
wire \Add0~231 ;
wire \Add0~231COUT1_256 ;
wire \Add0~232 ;
wire \addr[5]~reg0 ;
wire \Equal0~130 ;
wire \Add0~239 ;
wire \Add0~239COUT1_259 ;
wire \Add0~240 ;
wire \addr[9]~reg0 ;
wire \Add0~241 ;
wire \Add0~241COUT1_260 ;
wire \Add0~242 ;
wire \addr[10]~reg0 ;
wire \Add0~243 ;
wire \Add0~243COUT1_261 ;
wire \Add0~244 ;
wire \addr[11]~reg0 ;
wire \Add0~245 ;
wire \Add0~246 ;
wire \addr[12]~reg0 ;
wire \Add0~247 ;
wire \Add0~247COUT1_262 ;
wire \Add0~248 ;
wire \addr[13]~reg0 ;
wire \Add0~249 ;
wire \Add0~249COUT1_263 ;
wire \Add0~250 ;
wire \addr[14]~reg0 ;
wire \Equal1~188 ;
wire \Equal1~189 ;
wire \Equal0~131 ;
wire write;
wire \write_clk~combout ;
wire write_clk0;
wire write_clk1;
wire \drop~23 ;
wire drop;
wire \WE_hold~38 ;
wire \WE_hold~39 ;
wire \addr[7]~1384 ;
wire \addr[7]~1363 ;
wire \Add0~233 ;
wire \Add0~233COUT1_257 ;
wire \Add0~234 ;
wire \addr[6]~reg0 ;
wire \Add0~235 ;
wire \Add0~236 ;
wire \addr[7]~reg0 ;
wire \Add1~125 ;
wire \Add1~125COUT1_129 ;
wire \Add1~114 ;
wire \Add1~115 ;
wire \Add1~115COUT1_130 ;
wire \Add1~119 ;
wire \Add1~119COUT1 ;
wire \Add1~127 ;
wire \Add1~123 ;
wire \Add1~123COUT1_131 ;
wire \Add1~116 ;
wire \Equal1~190 ;
wire \Add1~118 ;
wire \Equal1~191 ;
wire \Add1~126 ;
wire \Add1~124 ;
wire \Equal1~193 ;
wire \Add1~117 ;
wire \Add1~117COUT1_132 ;
wire \Add1~120 ;
wire \Add1~122 ;
wire \Equal1~192 ;
wire \Equal1~194 ;
wire \Equal1~195 ;
wire \always0~3 ;
wire \OE~185 ;
wire \OE~186 ;
wire \OE~reg0 ;
wire \WE~656 ;
wire \WE~reg0 ;
wire mod;
wire \WE~658 ;
wire \WE~659 ;
wire read;
wire \data_in_temp[0]~275 ;
wire \data_out~80 ;
wire \data_out~81 ;
wire \data_out~82 ;
wire \data_out~83 ;
wire \data_out~84 ;
wire \data_out~85 ;
wire \data_out~86 ;
wire \data_out~87 ;
wire \req~138 ;
wire \req~139 ;
wire \req~140 ;
wire \req~reg0 ;
wire [1:0] WE_hold;
wire [7:0] \addr_in~combout ;
wire [7:0] \data_in~combout ;
wire [7:0] data_in_temp;
wire [7:0] data_temp;


// atom is at PIN_81
maxii_io \data_io[0]~I (
	.datain(\data_in~combout [0]),
	.oe(write),
	.combout(\data_io[0]~7 ),
	.padio(data_io[0]));
// synopsys translate_off
defparam \data_io[0]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_84
maxii_io \data_io[1]~I (
	.datain(\data_in~combout [1]),
	.oe(write),
	.combout(\data_io[1]~6 ),
	.padio(data_io[1]));
// synopsys translate_off
defparam \data_io[1]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_64
maxii_io \data_io[2]~I (
	.datain(\data_in~combout [2]),
	.oe(write),
	.combout(\data_io[2]~5 ),
	.padio(data_io[2]));
// synopsys translate_off
defparam \data_io[2]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_72
maxii_io \data_io[3]~I (
	.datain(\data_in~combout [3]),
	.oe(write),
	.combout(\data_io[3]~4 ),
	.padio(data_io[3]));
// synopsys translate_off
defparam \data_io[3]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_76
maxii_io \data_io[4]~I (
	.datain(\data_in~combout [4]),
	.oe(write),
	.combout(\data_io[4]~3 ),
	.padio(data_io[4]));
// synopsys translate_off
defparam \data_io[4]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_100
maxii_io \data_io[5]~I (
	.datain(\data_in~combout [5]),
	.oe(write),
	.combout(\data_io[5]~2 ),
	.padio(data_io[5]));
// synopsys translate_off
defparam \data_io[5]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_95
maxii_io \data_io[6]~I (
	.datain(\data_in~combout [6]),
	.oe(write),
	.combout(\data_io[6]~1 ),
	.padio(data_io[6]));
// synopsys translate_off
defparam \data_io[6]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_58
maxii_io \data_io[7]~I (
	.datain(\data_in~combout [7]),
	.oe(write),
	.combout(\data_io[7]~0 ),
	.padio(data_io[7]));
// synopsys translate_off
defparam \data_io[7]~I .operation_mode = "bidir";
// synopsys translate_on

// atom is at PIN_14
maxii_io \clk~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\clk~combout ),
	.padio(clk));
// synopsys translate_off
defparam \clk~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_89
maxii_io \rst~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\rst~combout ),
	.padio(rst));
// synopsys translate_off
defparam \rst~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X3_Y2_N5
maxii_lcell \CS~reg0_I (
// Equation(s):
// \CS~reg0  = DFFEAS(!\rst~combout , GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\rst~combout ),
	.datac(vcc),
	.datad(vcc),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(\CS~reg0 ),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \CS~reg0_I .lut_mask = "3333";
defparam \CS~reg0_I .operation_mode = "normal";
defparam \CS~reg0_I .output_mode = "reg_only";
defparam \CS~reg0_I .register_cascade_mode = "off";
defparam \CS~reg0_I .sum_lutc_input = "datac";
defparam \CS~reg0_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_35
maxii_io \mode~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\mode~combout ),
	.padio(mode));
// synopsys translate_off
defparam \mode~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_97
maxii_io \read_en~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\read_en~combout ),
	.padio(read_en));
// synopsys translate_off
defparam \read_en~I .operation_mode = "input";
// synopsys translate_on

// atom is at LC_X2_Y3_N9
maxii_lcell \read_en0~I (
// Equation(s):
// read_en0 = DFFEAS(\rst~combout  & (\read_en~combout ), GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\rst~combout ),
	.datac(vcc),
	.datad(\read_en~combout ),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(read_en0),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \read_en0~I .lut_mask = "CC00";
defparam \read_en0~I .operation_mode = "normal";
defparam \read_en0~I .output_mode = "reg_only";
defparam \read_en0~I .register_cascade_mode = "off";
defparam \read_en0~I .sum_lutc_input = "datac";
defparam \read_en0~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X2_Y3_N2
maxii_lcell \read_en1~I (
// Equation(s):
// read_en1 = DFFEAS(\rst~combout  & (read_en0), GLOBAL(\clk~combout ), VCC, , , , , , )

	.clk(\clk~combout ),
	.dataa(vcc),
	.datab(\rst~combout ),
	.datac(vcc),
	.datad(read_en0),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(),
	.regout(read_en1),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \read_en1~I .lut_mask = "CC00";
defparam \read_en1~I .operation_mode = "normal";
defparam \read_en1~I .output_mode = "reg_only";
defparam \read_en1~I .register_cascade_mode = "off";
defparam \read_en1~I .sum_lutc_input = "datac";
defparam \read_en1~I .synch_mode = "off";
// synopsys translate_on

// atom is at LC_X2_Y3_N8
maxii_lcell \addr[9]~1360_I (
// Equation(s):
// \addr[9]~1360  = !read_en0 & (read_en1)

	.clk(gnd),
	.dataa(vcc),
	.datab(read_en0),
	.datac(vcc),
	.datad(read_en1),
	.aclr(gnd),
	.aload(gnd),
	.sclr(gnd),
	.sload(gnd),
	.ena(vcc),
	.cin(gnd),
	.cin0(gnd),
	.cin1(vcc),
	.inverta(gnd),
	.regcascin(gnd),
	.devclrn(devclrn),
	.devpor(devpor),
	.combout(\addr[9]~1360 ),
	.regout(),
	.cout(),
	.cout0(),
	.cout1());
// synopsys translate_off
defparam \addr[9]~1360_I .lut_mask = "3300";
defparam \addr[9]~1360_I .operation_mode = "normal";
defparam \addr[9]~1360_I .output_mode = "comb_only";
defparam \addr[9]~1360_I .register_cascade_mode = "off";
defparam \addr[9]~1360_I .sum_lutc_input = "datac";
defparam \addr[9]~1360_I .synch_mode = "off";
// synopsys translate_on

// atom is at PIN_68
maxii_io \addr_in[7]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [7]),
	.padio(addr_in[7]));
// synopsys translate_off
defparam \addr_in[7]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_6
maxii_io \addr_in[6]~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\addr_in~combout [6]),
	.padio(addr_in[6]));
// synopsys translate_off
defparam \addr_in[6]~I .operation_mode = "input";
// synopsys translate_on

// atom is at PIN_26
maxii_io \write_en~I (
	.datain(gnd),
	.oe(gnd),
	.combout(\write_en~combout ),
	.padio(write_en));
// synopsys translate_off
defparam \write_en~I .operation_mode = "input";
// synopsys translate_on