entries

verilog实现的异步UART代码

/eth_clockgen.v/1.2/Tue Dec 13 12:54:49 2005//
/eth_outputcontrol.v/1.2/Tue Dec 13 12:54:49 2005//
/eth_shiftreg.v/1.2/Tue Dec 13 12:54:49 2005//
/timescale.v/1.2/Tue Dec 13 12:54:49 2005//
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