clk_div2.v

verilog实现的异步UART代码

//////////////////////////////////////////////////////////////////////
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////  CLK_DIV2.v                                                  ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
////                                                              ////
////  Author(s):                                                  ////
////      - Jon Gao ([e-mail])                            ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
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//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//                                                                    
// CVS Revision History                                               
//                                                                    
// $Log: CLK_DIV2.v,v $
// Revision 1.1  2006/10/22 16:12:25  maverickist
// no message
//
// Revision 1.1  2006/06/22 09:01:42  Administrator
// no message
//
// Revision 1.2  2005/12/16 06:44:20  Administrator
// replaced tab with space.
// passed 9.6k length frame test.
//
// Revision 1.1.1.1  2005/12/13 01:51:44  Administrator
// no message
// 


//////////////////////////////////////////////////////////////////////
// This file can only used for simulation .
// You need to replace it with your own element according to technology
//////////////////////////////////////////////////////////////////////

module CLK_DIV2 (
input       Reset,
input       IN,
output  reg OUT
);

always @ (posedge IN or posedge Reset)
    if (Reset)
        OUT     <=0;  
    else
        OUT     <=!OUT;    
    
endmodule