sele.vhdl

来自「相位差测试」· VHDL 代码 · 共 28 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sele is
      port(se1,se10,se100:	in	std_logic;
	      f1hz,f10hz,f100hz:	in	std_logic;
		 fref:			out	std_logic;
		 dp1,dp2,dp3:		out	std_logic);
end sele;
architecture Behavioral of sele is
begin
  process (se1,se10,se100,f1hz,f10hz,f100hz)
   begin
      fref <= '0'; dp1 <= '0';dp2 <= '0';dp3 <= '0';
      if se1 = '1' then
	 fref <= f1hz;
	 dp1<= '1';
      elsif se10 = '1' then
	 fref <= f10hz;
	 dp2 <= '1';
      elsif se100 = '1' then
	 fref <= f100hz;
	 dp3 <='1';
      end if;
   end process;
end Behavioral;