sd_top.hier_info

8读8写SDRAM verilog 程序

|sd_if|sd_top:sd_top1|sd_cnfg:u1
sdram_en => sdram_en1.DATAIN
clk => sdram_en2.CLK
clk => load_req~reg0.CLK
clk => charge_req~reg0.CLK
clk => fresh_req~reg0.CLK
clk => sdram_setup~reg0.CLK
clk => sdram_en1.CLK
clk => state~37.IN1
rst_l => load_req~reg0.ACLR
rst_l => charge_req~reg0.ACLR
rst_l => fresh_req~reg0.ACLR
rst_l => sdram_en2.ACLR
rst_l => sdram_en1.ACLR
rst_l => sdram_setup~reg0.ENA
rst_l => state~38.IN1
load_req <= load_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
charge_req <= charge_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
fresh_req <= fresh_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
load_cycle => state~30.OUTPUTSELECT
load_cycle => state~31.OUTPUTSELECT
load_cycle => state~32.OUTPUTSELECT
load_cycle => state~33.OUTPUTSELECT
load_cycle => state~34.OUTPUTSELECT
load_cycle => state~35.OUTPUTSELECT
load_cycle => state~36.OUTPUTSELECT
load_cycle => Selector7.IN1
fresh_cycle => state~14.OUTPUTSELECT
fresh_cycle => state~15.OUTPUTSELECT
fresh_cycle => state~16.OUTPUTSELECT
fresh_cycle => state~17.OUTPUTSELECT
fresh_cycle => state~18.OUTPUTSELECT
fresh_cycle => state~19.OUTPUTSELECT
fresh_cycle => state~20.OUTPUTSELECT
fresh_cycle => state~28.OUTPUTSELECT
fresh_cycle => state~29.OUTPUTSELECT
fresh_cycle => state~21.OUTPUTSELECT
fresh_cycle => state~22.OUTPUTSELECT
fresh_cycle => state~23.OUTPUTSELECT
fresh_cycle => state~24.OUTPUTSELECT
fresh_cycle => state~25.OUTPUTSELECT
fresh_cycle => state~26.OUTPUTSELECT
fresh_cycle => state~27.OUTPUTSELECT
fresh_cycle => Selector9.IN1
fresh_cycle => Selector9.IN2
charge_cycle => state~7.OUTPUTSELECT
charge_cycle => state~8.OUTPUTSELECT
charge_cycle => state~9.OUTPUTSELECT
charge_cycle => state~10.OUTPUTSELECT
charge_cycle => state~11.OUTPUTSELECT
charge_cycle => state~12.OUTPUTSELECT
charge_cycle => state~13.OUTPUTSELECT
charge_cycle => Selector8.IN1
sdram_setup <= sdram_setup~reg0.DB_MAX_OUTPUT_PORT_TYPE


|sd_if|sd_top:sd_top1|sd_state:u2
clk => sdram_cycle[3].CLK
clk => sdram_cycle[2].CLK
clk => sdram_cycle[1].CLK
clk => sdram_cycle[0].CLK
clk => charge_on.CLK
clk => sdram_cycle[4].CLK
rst_l => sdram_cycle[3].ACLR
rst_l => sdram_cycle[2].ACLR
rst_l => sdram_cycle[1].ACLR
rst_l => sdram_cycle[0].PRESET
rst_l => charge_on.ACLR
rst_l => sdram_cycle[4].ACLR
fresh_req => sdram_cycle~10.OUTPUTSELECT
fresh_req => sdram_cycle~11.OUTPUTSELECT
fresh_req => sdram_cycle~12.OUTPUTSELECT
fresh_req => sdram_cycle~13.OUTPUTSELECT
fresh_req => sdram_cycle~14.OUTPUTSELECT
load_req => sdram_cycle~5.OUTPUTSELECT
load_req => sdram_cycle~6.OUTPUTSELECT
load_req => sdram_cycle~7.OUTPUTSELECT
load_req => sdram_cycle~8.OUTPUTSELECT
load_req => sdram_cycle~9.OUTPUTSELECT
charge_req => always0~0.IN1
data_req => sdram_cycle~0.OUTPUTSELECT
data_req => sdram_cycle~1.OUTPUTSELECT
data_req => sdram_cycle~2.OUTPUTSELECT
data_req => sdram_cycle~3.OUTPUTSELECT
data_req => sdram_cycle~4.OUTPUTSELECT
data_req => Selector5.IN1
data_req => sdram_cycle~20.OUTPUTSELECT
data_req => sdram_cycle~21.OUTPUTSELECT
data_req => sdram_cycle~22.OUTPUTSELECT
data_req => sdram_cycle~23.OUTPUTSELECT
data_req => sdram_cycle~24.OUTPUTSELECT
idle_cycle <= sdram_cycle[0].DB_MAX_OUTPUT_PORT_TYPE
load_cycle <= sdram_cycle[1].DB_MAX_OUTPUT_PORT_TYPE
data_cycle <= sdram_cycle[2].DB_MAX_OUTPUT_PORT_TYPE
fresh_cycle <= sdram_cycle[3].DB_MAX_OUTPUT_PORT_TYPE
charge_cycle <= sdram_cycle[4].DB_MAX_OUTPUT_PORT_TYPE
state_cntr[0] => ~NO_FANOUT~
state_cntr[1] => ~NO_FANOUT~
state_cntr[2] => ~NO_FANOUT~
state_cntr[3] => sdram_cycle~25.OUTPUTSELECT
state_cntr[3] => sdram_cycle~26.OUTPUTSELECT
state_cntr[3] => sdram_cycle~27.OUTPUTSELECT
state_cntr[3] => sdram_cycle~28.OUTPUTSELECT
state_cntr[3] => sdram_cycle~29.OUTPUTSELECT
state_cntr[4] => ~NO_FANOUT~
state_cntr[5] => ~NO_FANOUT~
state_cntr[6] => ~NO_FANOUT~
state_cntr[7] => ~NO_FANOUT~


|sd_if|sd_top:sd_top1|sd_rfrsh:u3
clk => rfrsh_cntr[9].CLK
clk => rfrsh_cntr[8].CLK
clk => rfrsh_cntr[7].CLK
clk => rfrsh_cntr[6].CLK
clk => rfrsh_cntr[5].CLK
clk => rfrsh_cntr[4].CLK
clk => rfrsh_cntr[3].CLK
clk => rfrsh_cntr[2].CLK
clk => rfrsh_cntr[1].CLK
clk => rfrsh_cntr[0].CLK
clk => fresh_req~reg0.CLK
clk => rfrsh_cntr[10].CLK
rst_l => rfrsh_cntr[9].ACLR
rst_l => rfrsh_cntr[8].ACLR
rst_l => rfrsh_cntr[7].ACLR
rst_l => rfrsh_cntr[6].ACLR
rst_l => rfrsh_cntr[5].ACLR
rst_l => rfrsh_cntr[4].ACLR
rst_l => rfrsh_cntr[3].ACLR
rst_l => rfrsh_cntr[2].ACLR
rst_l => rfrsh_cntr[1].ACLR
rst_l => rfrsh_cntr[0].ACLR
rst_l => fresh_req~reg0.ACLR
rst_l => rfrsh_cntr[10].ACLR
fresh_cycle => rfrsh_cntr~0.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~1.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~2.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~3.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~4.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~5.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~6.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~7.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~8.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~9.OUTPUTSELECT
fresh_cycle => rfrsh_cntr~10.OUTPUTSELECT
fresh_cycle => fresh_req~1.OUTPUTSELECT
fresh_req <= fresh_req~reg0.DB_MAX_OUTPUT_PORT_TYPE


|sd_if|sd_top:sd_top1|sd_sig:u4
rst_l => sd_add[10]~reg0.PRESET
rst_l => sd_add[9]~reg0.ACLR
rst_l => sd_add[8]~reg0.ACLR
rst_l => sd_add[7]~reg0.ACLR
rst_l => sd_add[6]~reg0.ACLR
rst_l => sd_add[5]~reg0.ACLR
rst_l => sd_add[4]~reg0.ACLR
rst_l => sd_add[3]~reg0.ACLR
rst_l => sd_add[2]~reg0.ACLR
rst_l => sd_add[1]~reg0.ACLR
rst_l => sd_add[0]~reg0.ACLR
rst_l => sd_ba[0]~reg0.ACLR
rst_l => sd_add[11]~reg0.ACLR
rst_l => sd_ba[1]~reg0.ACLR
rst_l => sd_cs0_l~reg0.PRESET
rst_l => sd_ras_l~reg0.PRESET
rst_l => sd_cas_l~reg0.PRESET
rst_l => sd_we_l~reg0.PRESET
rst_l => sd_cke~reg0.ACLR
rst_l => sd_dqm[14]~reg0.ACLR
rst_l => sd_dqm[13]~reg0.ACLR
rst_l => sd_dqm[12]~reg0.ACLR
rst_l => sd_dqm[11]~reg0.ACLR
rst_l => sd_dqm[10]~reg0.ACLR
rst_l => sd_dqm[9]~reg0.ACLR
rst_l => sd_dqm[8]~reg0.ACLR
rst_l => sd_dqm[7]~reg0.ACLR
rst_l => sd_dqm[6]~reg0.ACLR
rst_l => sd_dqm[5]~reg0.ACLR
rst_l => sd_dqm[4]~reg0.ACLR
rst_l => sd_dqm[3]~reg0.ACLR
rst_l => sd_dqm[2]~reg0.ACLR
rst_l => sd_dqm[1]~reg0.ACLR
rst_l => sd_dqm[0]~reg0.ACLR
rst_l => sd_dqm[15]~reg0.ACLR
clk => sd_add[10]~reg0.CLK
clk => sd_add[9]~reg0.CLK
clk => sd_add[8]~reg0.CLK
clk => sd_add[7]~reg0.CLK
clk => sd_add[6]~reg0.CLK
clk => sd_add[5]~reg0.CLK
clk => sd_add[4]~reg0.CLK
clk => sd_add[3]~reg0.CLK
clk => sd_add[2]~reg0.CLK
clk => sd_add[1]~reg0.CLK
clk => sd_add[0]~reg0.CLK
clk => sd_ba[1]~reg0.CLK
clk => sd_ba[0]~reg0.CLK
clk => sd_cs0_l~reg0.CLK
clk => sd_ras_l~reg0.CLK
clk => sd_cas_l~reg0.CLK
clk => sd_we_l~reg0.CLK
clk => sd_cke~reg0.CLK
clk => sd_dqm[15]~reg0.CLK
clk => sd_dqm[14]~reg0.CLK
clk => sd_dqm[13]~reg0.CLK
clk => sd_dqm[12]~reg0.CLK
clk => sd_dqm[11]~reg0.CLK
clk => sd_dqm[10]~reg0.CLK
clk => sd_dqm[9]~reg0.CLK
clk => sd_dqm[8]~reg0.CLK
clk => sd_dqm[7]~reg0.CLK
clk => sd_dqm[6]~reg0.CLK
clk => sd_dqm[5]~reg0.CLK
clk => sd_dqm[4]~reg0.CLK
clk => sd_dqm[3]~reg0.CLK
clk => sd_dqm[2]~reg0.CLK
clk => sd_dqm[1]~reg0.CLK
clk => sd_dqm[0]~reg0.CLK
clk => state_cntr[7]~reg0.CLK
clk => state_cntr[6]~reg0.CLK
clk => state_cntr[5]~reg0.CLK
clk => state_cntr[4]~reg0.CLK
clk => state_cntr[3]~reg0.CLK
clk => state_cntr[2]~reg0.CLK
clk => state_cntr[1]~reg0.CLK
clk => state_cntr[0]~reg0.CLK
clk => sd_add[11]~reg0.CLK
add[0] => ~NO_FANOUT~
add[1] => ~NO_FANOUT~
add[2] => ~NO_FANOUT~
add[3] => ~NO_FANOUT~
add[4] => sd_add~7.DATAB
add[5] => sd_add~6.DATAB
add[6] => sd_add~5.DATAB
add[7] => sd_add~4.DATAB
add[8] => sd_add~3.DATAB
add[9] => sd_add~2.DATAB
add[10] => sd_add~1.DATAB
add[11] => sd_add~0.DATAB
add[12] => sd_add~18.DATAB
add[13] => sd_add~17.DATAB
add[14] => sd_add~16.DATAB
add[15] => sd_add~15.DATAB
add[16] => sd_add~14.DATAB
add[17] => sd_add~13.DATAB
add[18] => sd_add~12.DATAB
add[19] => sd_add~11.DATAB
add[20] => sd_add~10.DATAB
add[21] => sd_add~9.DATAB
add[22] => sd_add~8.DATAB
add[23] => sd_ba~1.DATAB
add[23] => sd_ba~3.DATAB
add[23] => sd_ba~5.DATAB
add[24] => sd_ba~0.DATAB
add[24] => sd_ba~2.DATAB
add[24] => sd_ba~4.DATAB
wr_l => always5~0.IN1
byte_en[0] => sd_dqm~15.DATAB
byte_en[1] => sd_dqm~14.DATAB
byte_en[2] => sd_dqm~13.DATAB
byte_en[3] => sd_dqm~12.DATAB
byte_en[4] => sd_dqm~11.DATAB
byte_en[5] => sd_dqm~10.DATAB
byte_en[6] => sd_dqm~9.DATAB
byte_en[7] => sd_dqm~8.DATAB
byte_en[8] => sd_dqm~7.DATAB
byte_en[9] => sd_dqm~6.DATAB
byte_en[10] => sd_dqm~5.DATAB
byte_en[11] => sd_dqm~4.DATAB
byte_en[12] => sd_dqm~3.DATAB
byte_en[13] => sd_dqm~2.DATAB
byte_en[14] => sd_dqm~1.DATAB
byte_en[15] => sd_dqm~0.DATAB
idle_cycle => state_cntr~0.OUTPUTSELECT
idle_cycle => state_cntr~1.OUTPUTSELECT
idle_cycle => state_cntr~2.OUTPUTSELECT
idle_cycle => state_cntr~3.OUTPUTSELECT
idle_cycle => state_cntr~4.OUTPUTSELECT
idle_cycle => state_cntr~5.OUTPUTSELECT
idle_cycle => state_cntr~6.OUTPUTSELECT
idle_cycle => state_cntr[0]~reg0.DATAIN
load_cycle => always0~0.IN1
load_cycle => sd_cs0_l~3.OUTPUTSELECT
data_cycle => always0~1.IN1
data_cycle => always0~2.IN0
data_cycle => sd_cs0_l~1.OUTPUTSELECT
data_cycle => sd_cs0_l~2.OUTPUTSELECT
data_cycle => always5~0.IN0
fresh_cycle => always3~0.IN1
fresh_cycle => sd_cs0_l~0.DATAA
charge_cycle => always1~0.IN1
charge_cycle => sd_cs0_l~0.OUTPUTSELECT
state_cntr[0] <= state_cntr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[1] <= state_cntr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[2] <= state_cntr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[3] <= state_cntr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[4] <= state_cntr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[5] <= state_cntr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[6] <= state_cntr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[7] <= state_cntr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[0] <= sd_add[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[1] <= sd_add[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[2] <= sd_add[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[3] <= sd_add[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[4] <= sd_add[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[5] <= sd_add[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[6] <= sd_add[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[7] <= sd_add[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[8] <= sd_add[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[9] <= sd_add[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[10] <= sd_add[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_add[11] <= sd_add[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_ba[0] <= sd_ba[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_ba[1] <= sd_ba[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_cs0_l <= sd_cs0_l~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_ras_l <= sd_ras_l~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_cas_l <= sd_cas_l~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_we_l <= sd_we_l~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_cke <= sd_cke~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[0] <= sd_dqm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[1] <= sd_dqm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[2] <= sd_dqm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[3] <= sd_dqm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[4] <= sd_dqm[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[5] <= sd_dqm[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[6] <= sd_dqm[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[7] <= sd_dqm[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[8] <= sd_dqm[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[9] <= sd_dqm[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[10] <= sd_dqm[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[11] <= sd_dqm[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[12] <= sd_dqm[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[13] <= sd_dqm[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[14] <= sd_dqm[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sd_dqm[15] <= sd_dqm[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rs_ready => always0~2.IN1
rs_ready => always5~1.IN0