sd_top.hier_info

8读8写SDRAM verilog 程序

|sd_if
ch_req => ch_req~0.IN1
ch_addr[0] => ch_addr[0]~20.IN1
ch_addr[1] => ch_addr[1]~19.IN1
ch_addr[2] => ch_addr[2]~18.IN1
ch_addr[3] => ch_addr[3]~17.IN1
ch_addr[4] => ch_addr[4]~16.IN1
ch_addr[5] => ch_addr[5]~15.IN1
ch_addr[6] => ch_addr[6]~14.IN1
ch_addr[7] => ch_addr[7]~13.IN1
ch_addr[8] => ch_addr[8]~12.IN1
ch_addr[9] => ch_addr[9]~11.IN1
ch_addr[10] => ch_addr[10]~10.IN1
ch_addr[11] => ch_addr[11]~9.IN1
ch_addr[12] => ch_addr[12]~8.IN1
ch_addr[13] => ch_addr[13]~7.IN1
ch_addr[14] => ch_addr[14]~6.IN1
ch_addr[15] => ch_addr[15]~5.IN1
ch_addr[16] => ch_addr[16]~4.IN1
ch_addr[17] => ch_addr[17]~3.IN1
ch_addr[18] => ch_addr[18]~2.IN1
ch_addr[19] => ch_addr[19]~1.IN1
ch_addr[20] => ch_addr[20]~0.IN1
ch_rw => ch_rw~0.IN1
ch_num[0] => ch_num[0]~7.IN1
ch_num[1] => ch_num[1]~6.IN1
ch_num[2] => ch_num[2]~5.IN1
ch_num[3] => ch_num[3]~4.IN1
ch_num[4] => ch_num[4]~3.IN1
ch_num[5] => ch_num[5]~2.IN1
ch_num[6] => ch_num[6]~1.IN1
ch_num[7] => ch_num[7]~0.IN1
ch_ack <= rw_sd_mach:u1.ch_ack
ch_dqm[0] => ch_dqm[0]~15.IN1
ch_dqm[1] => ch_dqm[1]~14.IN1
ch_dqm[2] => ch_dqm[2]~13.IN1
ch_dqm[3] => ch_dqm[3]~12.IN1
ch_dqm[4] => ch_dqm[4]~11.IN1
ch_dqm[5] => ch_dqm[5]~10.IN1
ch_dqm[6] => ch_dqm[6]~9.IN1
ch_dqm[7] => ch_dqm[7]~8.IN1
ch_dqm[8] => ch_dqm[8]~7.IN1
ch_dqm[9] => ch_dqm[9]~6.IN1
ch_dqm[10] => ch_dqm[10]~5.IN1
ch_dqm[11] => ch_dqm[11]~4.IN1
ch_dqm[12] => ch_dqm[12]~3.IN1
ch_dqm[13] => ch_dqm[13]~2.IN1
ch_dqm[14] => ch_dqm[14]~1.IN1
ch_dqm[15] => ch_dqm[15]~0.IN1
dp_addr[0] <= rw_sd_mach:u1.dp_addr
dp_addr[1] <= rw_sd_mach:u1.dp_addr
dp_addr[2] <= rw_sd_mach:u1.dp_addr
dp_addr[3] <= rw_sd_mach:u1.dp_addr
dp_addr[4] <= rw_sd_mach:u1.dp_addr
dp_addr[5] <= rw_sd_mach:u1.dp_addr
dp_addr[6] <= rw_sd_mach:u1.dp_addr
dp_addr[7] <= rw_sd_mach:u1.dp_addr
dp_wren <= rw_sd_mach:u1.dp_wren
dp_rden <= rw_sd_mach:u1.dp_rden
clk => clk~0.IN2
rst_l => rst_l~0.IN2
sdram_en => sdram_en~0.IN1
sd_cke <= sd_top:sd_top1.sd_cke
sd_ba[0] <= sd_top:sd_top1.sd_ba
sd_ba[1] <= sd_top:sd_top1.sd_ba
sd_cs0_l <= sd_top:sd_top1.sd_cs0_l
sd_ras_l <= sd_top:sd_top1.sd_ras_l
sd_cas_l <= sd_top:sd_top1.sd_cas_l
sd_we_l <= sd_top:sd_top1.sd_we_l
sd_add[0] <= sd_top:sd_top1.sd_add
sd_add[1] <= sd_top:sd_top1.sd_add
sd_add[2] <= sd_top:sd_top1.sd_add
sd_add[3] <= sd_top:sd_top1.sd_add
sd_add[4] <= sd_top:sd_top1.sd_add
sd_add[5] <= sd_top:sd_top1.sd_add
sd_add[6] <= sd_top:sd_top1.sd_add
sd_add[7] <= sd_top:sd_top1.sd_add
sd_add[8] <= sd_top:sd_top1.sd_add
sd_add[9] <= sd_top:sd_top1.sd_add
sd_add[10] <= sd_top:sd_top1.sd_add
sd_dqm[0] <= sd_top:sd_top1.sd_dqm
sd_dqm[1] <= sd_top:sd_top1.sd_dqm
sd_dqm[2] <= sd_top:sd_top1.sd_dqm
sd_dqm[3] <= sd_top:sd_top1.sd_dqm
sd_dqm[4] <= sd_top:sd_top1.sd_dqm
sd_dqm[5] <= sd_top:sd_top1.sd_dqm
sd_dqm[6] <= sd_top:sd_top1.sd_dqm
sd_dqm[7] <= sd_top:sd_top1.sd_dqm
sd_dqm[8] <= sd_top:sd_top1.sd_dqm
sd_dqm[9] <= sd_top:sd_top1.sd_dqm
sd_dqm[10] <= sd_top:sd_top1.sd_dqm
sd_dqm[11] <= sd_top:sd_top1.sd_dqm
sd_dqm[12] <= sd_top:sd_top1.sd_dqm
sd_dqm[13] <= sd_top:sd_top1.sd_dqm
sd_dqm[14] <= sd_top:sd_top1.sd_dqm
sd_dqm[15] <= sd_top:sd_top1.sd_dqm
sdram_setup <= sdram_setup~0.DB_MAX_OUTPUT_PORT_TYPE
rs_ready <= rs_ready~0.DB_MAX_OUTPUT_PORT_TYPE


|sd_if|rw_sd_mach:u1
clk => op_num[7].CLK
clk => op_num[6].CLK
clk => op_num[5].CLK
clk => op_num[4].CLK
clk => op_num[3].CLK
clk => op_num[2].CLK
clk => op_num[1].CLK
clk => op_num[0].CLK
clk => op_active.CLK
clk => op_over.CLK
clk => rs_ready~reg0.CLK
clk => rs_ready_delay[4].CLK
clk => rs_ready_delay[3].CLK
clk => rs_ready_delay[2].CLK
clk => rs_ready_delay[1].CLK
clk => rs_ready_delay[0].CLK
clk => dp_addr[7]~reg0.CLK
clk => dp_addr[6]~reg0.CLK
clk => dp_addr[5]~reg0.CLK
clk => dp_addr[4]~reg0.CLK
clk => dp_addr[3]~reg0.CLK
clk => dp_addr[2]~reg0.CLK
clk => dp_addr[1]~reg0.CLK
clk => dp_addr[0]~reg0.CLK
clk => add[24]~reg0.CLK
clk => add[23]~reg0.CLK
clk => add[22]~reg0.CLK
clk => add[21]~reg0.CLK
clk => add[20]~reg0.CLK
clk => add[19]~reg0.CLK
clk => add[18]~reg0.CLK
clk => add[17]~reg0.CLK
clk => add[16]~reg0.CLK
clk => add[15]~reg0.CLK
clk => add[14]~reg0.CLK
clk => add[13]~reg0.CLK
clk => add[12]~reg0.CLK
clk => add[11]~reg0.CLK
clk => add[10]~reg0.CLK
clk => add[9]~reg0.CLK
clk => add[8]~reg0.CLK
clk => add[7]~reg0.CLK
clk => add[6]~reg0.CLK
clk => add[5]~reg0.CLK
clk => add[4]~reg0.CLK
clk => add[3]~reg0.CLK
clk => add[2]~reg0.CLK
clk => add[1]~reg0.CLK
clk => add[0]~reg0.CLK
clk => op_en.CLK
rst_l => ~NO_FANOUT~
ch_req => data_req~0.IN0
ch_addr[0] => add~20.DATAA
ch_addr[1] => add~19.DATAA
ch_addr[2] => add~18.DATAA
ch_addr[3] => add~17.DATAA
ch_addr[4] => add~16.DATAA
ch_addr[5] => add~15.DATAA
ch_addr[6] => add~14.DATAA
ch_addr[7] => add~13.DATAA
ch_addr[8] => add~12.DATAA
ch_addr[9] => add~11.DATAA
ch_addr[10] => add~10.DATAA
ch_addr[11] => add~9.DATAA
ch_addr[12] => add~8.DATAA
ch_addr[13] => add~7.DATAA
ch_addr[14] => add~6.DATAA
ch_addr[15] => add~5.DATAA
ch_addr[16] => add~4.DATAA
ch_addr[17] => add~3.DATAA
ch_addr[18] => add~2.DATAA
ch_addr[19] => add~1.DATAA
ch_addr[20] => add~0.DATAA
ch_rw => dp_wren~0.IN1
ch_rw => wr_l.DATAIN
ch_rw => dp_rden~0.IN1
ch_num[0] => LessThan0.IN8
ch_num[1] => LessThan0.IN7
ch_num[2] => LessThan0.IN6
ch_num[3] => LessThan0.IN5
ch_num[4] => LessThan0.IN4
ch_num[5] => LessThan0.IN3
ch_num[6] => LessThan0.IN2
ch_num[7] => LessThan0.IN1
ch_ack <= op_over.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[0] <= dp_addr[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[1] <= dp_addr[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[2] <= dp_addr[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[3] <= dp_addr[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[4] <= dp_addr[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[5] <= dp_addr[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[6] <= dp_addr[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_addr[7] <= dp_addr[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dp_wren <= dp_wren~0.DB_MAX_OUTPUT_PORT_TYPE
dp_rden <= dp_rden~0.DB_MAX_OUTPUT_PORT_TYPE
data_req <= data_req~0.DB_MAX_OUTPUT_PORT_TYPE
add[0] <= add[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[1] <= add[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[2] <= add[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[3] <= add[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[4] <= add[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[5] <= add[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[6] <= add[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[7] <= add[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[8] <= add[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[9] <= add[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[10] <= add[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[11] <= add[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[12] <= add[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[13] <= add[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[14] <= add[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[15] <= add[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[16] <= add[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[17] <= add[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[18] <= add[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[19] <= add[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[20] <= add[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[21] <= add[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[22] <= add[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[23] <= add[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
add[24] <= add[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
wr_l <= ch_rw.DB_MAX_OUTPUT_PORT_TYPE
rs_ready <= rs_ready~reg0.DB_MAX_OUTPUT_PORT_TYPE
sdram_setup => data_req~0.IN1
data_cycle => op_en~1.OUTPUTSELECT
data_cycle => op_num~16.OUTPUTSELECT
data_cycle => op_num~17.OUTPUTSELECT
data_cycle => op_num~18.OUTPUTSELECT
data_cycle => op_num~19.OUTPUTSELECT
data_cycle => op_num~20.OUTPUTSELECT
data_cycle => op_num~21.OUTPUTSELECT
data_cycle => op_num~22.OUTPUTSELECT
data_cycle => op_num~23.OUTPUTSELECT
data_cycle => op_active~0.OUTPUTSELECT
data_cycle => op_over~2.OUTPUTSELECT
data_cycle => dp_rden~0.IN0
data_cycle => rs_ready_delay~0.OUTPUTSELECT
data_cycle => rs_ready_delay~1.OUTPUTSELECT
data_cycle => rs_ready_delay~2.OUTPUTSELECT
data_cycle => rs_ready_delay~3.OUTPUTSELECT
data_cycle => rs_ready_delay~4.OUTPUTSELECT
state_cntr[0] => op_en~0.OUTPUTSELECT
state_cntr[1] => ~NO_FANOUT~
state_cntr[2] => ~NO_FANOUT~
state_cntr[3] => ~NO_FANOUT~
state_cntr[4] => ~NO_FANOUT~
state_cntr[5] => ~NO_FANOUT~
state_cntr[6] => ~NO_FANOUT~
state_cntr[7] => ~NO_FANOUT~


|sd_if|sd_top:sd_top1
data_req => data_req~0.IN1
wr_l => wr_l~0.IN1
sdram_en => sdram_en~0.IN1
clk => clk~0.IN4
rst_l => rst_l~0.IN4
byte_en[0] => byte_en[0]~15.IN1
byte_en[1] => byte_en[1]~14.IN1
byte_en[2] => byte_en[2]~13.IN1
byte_en[3] => byte_en[3]~12.IN1
byte_en[4] => byte_en[4]~11.IN1
byte_en[5] => byte_en[5]~10.IN1
byte_en[6] => byte_en[6]~9.IN1
byte_en[7] => byte_en[7]~8.IN1
byte_en[8] => byte_en[8]~7.IN1
byte_en[9] => byte_en[9]~6.IN1
byte_en[10] => byte_en[10]~5.IN1
byte_en[11] => byte_en[11]~4.IN1
byte_en[12] => byte_en[12]~3.IN1
byte_en[13] => byte_en[13]~2.IN1
byte_en[14] => byte_en[14]~1.IN1
byte_en[15] => byte_en[15]~0.IN1
add[0] => add[0]~24.IN1
add[1] => add[1]~23.IN1
add[2] => add[2]~22.IN1
add[3] => add[3]~21.IN1
add[4] => add[4]~20.IN1
add[5] => add[5]~19.IN1
add[6] => add[6]~18.IN1
add[7] => add[7]~17.IN1
add[8] => add[8]~16.IN1
add[9] => add[9]~15.IN1
add[10] => add[10]~14.IN1
add[11] => add[11]~13.IN1
add[12] => add[12]~12.IN1
add[13] => add[13]~11.IN1
add[14] => add[14]~10.IN1
add[15] => add[15]~9.IN1
add[16] => add[16]~8.IN1
add[17] => add[17]~7.IN1
add[18] => add[18]~6.IN1
add[19] => add[19]~5.IN1
add[20] => add[20]~4.IN1
add[21] => add[21]~3.IN1
add[22] => add[22]~2.IN1
add[23] => add[23]~1.IN1
add[24] => add[24]~0.IN1
sd_cke <= sd_sig:u4.sd_cke
sd_ba[0] <= sd_sig:u4.sd_ba
sd_ba[1] <= sd_sig:u4.sd_ba
sd_cs0_l <= sd_sig:u4.sd_cs0_l
sd_ras_l <= sd_sig:u4.sd_ras_l
sd_cas_l <= sd_sig:u4.sd_cas_l
sd_we_l <= sd_sig:u4.sd_we_l
sd_add[0] <= sd_sig:u4.sd_add
sd_add[1] <= sd_sig:u4.sd_add
sd_add[2] <= sd_sig:u4.sd_add
sd_add[3] <= sd_sig:u4.sd_add
sd_add[4] <= sd_sig:u4.sd_add
sd_add[5] <= sd_sig:u4.sd_add
sd_add[6] <= sd_sig:u4.sd_add
sd_add[7] <= sd_sig:u4.sd_add
sd_add[8] <= sd_sig:u4.sd_add
sd_add[9] <= sd_sig:u4.sd_add
sd_add[10] <= sd_sig:u4.sd_add
sd_add[11] <= sd_sig:u4.sd_add
sd_dqm[0] <= sd_sig:u4.sd_dqm
sd_dqm[1] <= sd_sig:u4.sd_dqm
sd_dqm[2] <= sd_sig:u4.sd_dqm
sd_dqm[3] <= sd_sig:u4.sd_dqm
sd_dqm[4] <= sd_sig:u4.sd_dqm
sd_dqm[5] <= sd_sig:u4.sd_dqm
sd_dqm[6] <= sd_sig:u4.sd_dqm
sd_dqm[7] <= sd_sig:u4.sd_dqm
sd_dqm[8] <= sd_sig:u4.sd_dqm
sd_dqm[9] <= sd_sig:u4.sd_dqm
sd_dqm[10] <= sd_sig:u4.sd_dqm
sd_dqm[11] <= sd_sig:u4.sd_dqm
sd_dqm[12] <= sd_sig:u4.sd_dqm
sd_dqm[13] <= sd_sig:u4.sd_dqm
sd_dqm[14] <= sd_sig:u4.sd_dqm
sd_dqm[15] <= sd_sig:u4.sd_dqm
sdram_setup <= sd_cnfg:u1.sdram_setup
rs_ready => rs_ready~0.IN1
data_cycle <= data_cycle~0.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[0] <= state_cntr[0]~7.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[1] <= state_cntr[1]~6.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[2] <= state_cntr[2]~5.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[3] <= state_cntr[3]~4.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[4] <= state_cntr[4]~3.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[5] <= state_cntr[5]~2.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[6] <= state_cntr[6]~1.DB_MAX_OUTPUT_PORT_TYPE
state_cntr[7] <= state_cntr[7]~0.DB_MAX_OUTPUT_PORT_TYPE