sd_top.sim.qmsg

8读8写SDRAM verilog 程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jan 24 19:48:35 2008 " "Info: Processing started: Thu Jan 24 19:48:35 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off sd_top -c sd_top " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off sd_top -c sd_top" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "byte_en10 " "Warning: Ignored node in vector source file. Can't find corresponding node name \"byte_en10\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "byte_en10" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "add20 " "Warning: Ignored node in vector source file. Can't find corresponding node name \"add20\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "add20" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "add10 " "Warning: Ignored node in vector source file. Can't find corresponding node name \"add10\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "add10" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "sd_dqm10 " "Warning: Ignored node in vector source file. Can't find corresponding node name \"sd_dqm10\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "sd_dqm10" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "sd_add10 " "Warning: Ignored node in vector source file. Can't find corresponding node name \"sd_add10\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "sd_add10" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "\|sd_cnfg:u1\|state3.Q " "Warning: Ignored node in vector source file. Can't find corresponding node name \"\|sd_cnfg:u1\|state3.Q\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "\|sd_cnfg:u1\|state3.Q" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "\|sd_cnfg:u1\|state2.Q " "Warning: Ignored node in vector source file. Can't find corresponding node name \"\|sd_cnfg:u1\|state2.Q\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "\|sd_cnfg:u1\|state2.Q" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "\|sd_cnfg:u1\|state1.Q " "Warning: Ignored node in vector source file. Can't find corresponding node name \"\|sd_cnfg:u1\|state1.Q\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "\|sd_cnfg:u1\|state1.Q" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_INAME_FOR_CHANNEL" "\|sd_cnfg:u1\|state0.Q " "Warning: Ignored node in vector source file. Can't find corresponding node name \"\|sd_cnfg:u1\|state0.Q\" in design." {  } { { "D:/newsdram/sd_top.scf" "" { Waveform "D:/newsdram/sd_top.scf" "\|sd_cnfg:u1\|state0.Q" "0 ps" "0 ps" "" } }  } 0 0 "Ignored node in vector source file. Can't find corresponding node name \"%1!s!\" in design." 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|add\[0\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|add\[0\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|add\[1\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|add\[1\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|add\[2\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|add\[2\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|add\[3\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|add\[3\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|add\[20\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|add\[20\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|byte_en\[10\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|byte_en\[10\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Warning" "WSIM_NO_CHANNEL_FOUND" "\|sd_top\|add\[10\] " "Warning: Can't find signal in vector source file for input pin \"\|sd_top\|add\[10\]\"" {  } {  } 0 0 "Can't find signal in vector source file for input pin \"%1!s!\"" 0 0}
{ "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_FOUND" "" "Info: Inverted registers were found during simulation" { { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|sd_top\|sd_sig:u4\|sd_cs0_l " "Info: Register: \|sd_top\|sd_sig:u4\|sd_cs0_l" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|sd_top\|sd_sig:u4\|sd_ras_l " "Info: Register: \|sd_top\|sd_sig:u4\|sd_ras_l" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|sd_top\|sd_sig:u4\|sd_cas_l " "Info: Register: \|sd_top\|sd_sig:u4\|sd_cas_l" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|sd_top\|sd_sig:u4\|sd_we_l " "Info: Register: \|sd_top\|sd_sig:u4\|sd_we_l" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|sd_top\|sd_sig:u4\|sd_add\[10\] " "Info: Register: \|sd_top\|sd_sig:u4\|sd_add\[10\]" {  } {  } 0 0 "Register: %1!s!" 0 0} { "Info" "ISIM_SIM_INVERTED_REGISTER_OUTPUT_NAME" "\|sd_top\|sd_state:u2\|sdram_cycle\[0\] " "Info: Register: \|sd_top\|sd_state:u2\|sdram_cycle\[0\]" {  } {  } 0 0 "Register: %1!s!" 0 0}  } {  } 0 0 "Inverted registers were found during simulation" 0 0}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." {  } {  } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0}  } {  } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" {  } {  } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" "     45.58 % " "Info: Simulation coverage is      45.58 %" {  } {  } 0 0 "Simulation coverage is %1!s!" 0 0}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "1198 " "Info: Number of transitions in simulation is 1198" {  } {  } 0 0 "Number of transitions in simulation is %1!s!" 0 0}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "sd_top.sim.vwf " "Info: Vector file sd_top.sim.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." {  } {  } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 16 s Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 16 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 24 19:48:36 2008 " "Info: Processing ended: Thu Jan 24 19:48:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}