sd_top.tan.qmsg

8读8写SDRAM verilog 程序

{ "Info" "ITDB_TH_RESULT" "rw_sd_mach:u1\|add\[24\] ch_addr\[20\] clk 0.900 ns register " "Info: th for register \"rw_sd_mach:u1\|add\[24\]\" (data pin = \"ch_addr\[20\]\", clock pin = \"clk\") is 0.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_55 82 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_55; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns rw_sd_mach:u1\|add\[24\] 2 REG LC1_C8 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C8; Fanout = 1; REG Node = 'rw_sd_mach:u1\|add\[24\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clk rw_sd_mach:u1|add[24] } "NODE_NAME" } } { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk rw_sd_mach:u1|add[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out rw_sd_mach:u1|add[24] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "1.400 ns + " "Info: + Micro hold delay of destination is 1.400 ns" {  } { { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 102 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.400 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns ch_addr\[20\] 1 PIN PIN_125 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_125; Fanout = 1; PIN Node = 'ch_addr\[20\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ch_addr[20] } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(0.900 ns) 4.400 ns rw_sd_mach:u1\|add\[24\] 2 REG LC1_C8 1 " "Info: 2: + IC(1.600 ns) + CELL(0.900 ns) = 4.400 ns; Loc. = LC1_C8; Fanout = 1; REG Node = 'rw_sd_mach:u1\|add\[24\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.500 ns" { ch_addr[20] rw_sd_mach:u1|add[24] } "NODE_NAME" } } { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 102 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 63.64 % ) " "Info: Total cell delay = 2.800 ns ( 63.64 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.600 ns ( 36.36 % ) " "Info: Total interconnect delay = 1.600 ns ( 36.36 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { ch_addr[20] rw_sd_mach:u1|add[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.400 ns" { ch_addr[20] ch_addr[20]~out rw_sd_mach:u1|add[24] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.900ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk rw_sd_mach:u1|add[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out rw_sd_mach:u1|add[24] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.400 ns" { ch_addr[20] rw_sd_mach:u1|add[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.400 ns" { ch_addr[20] ch_addr[20]~out rw_sd_mach:u1|add[24] } { 0.000ns 0.000ns 1.600ns } { 0.000ns 1.900ns 0.900ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jan 24 21:35:20 2008 " "Info: Processing ended: Thu Jan 24 21:35:20 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}