sd_top.tan.qmsg

8读8写SDRAM verilog 程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 19 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sd_top:sd_top1\|sd_cnfg:u1\|fresh_req register sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[1\] 78.74 MHz 12.7 ns Internal " "Info: Clock \"clk\" has Internal fmax of 78.74 MHz between source register \"sd_top:sd_top1\|sd_cnfg:u1\|fresh_req\" and destination register \"sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[1\]\" (period= 12.7 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.500 ns + Longest register register " "Info: + Longest register to register delay is 10.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sd_top:sd_top1\|sd_cnfg:u1\|fresh_req 1 REG LC5_C15 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_C15; Fanout = 4; REG Node = 'sd_top:sd_top1\|sd_cnfg:u1\|fresh_req'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sd_top:sd_top1|sd_cnfg:u1|fresh_req } "NODE_NAME" } } { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(1.900 ns) 3.700 ns sd_top:sd_top1\|sd_state:u2\|Selector2~111 2 COMB LC1_C13 3 " "Info: 2: + IC(1.800 ns) + CELL(1.900 ns) = 3.700 ns; Loc. = LC1_C13; Fanout = 3; COMB Node = 'sd_top:sd_top1\|sd_state:u2\|Selector2~111'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.700 ns" { sd_top:sd_top1|sd_cnfg:u1|fresh_req sd_top:sd_top1|sd_state:u2|Selector2~111 } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(1.400 ns) 7.000 ns sd_top:sd_top1\|sd_state:u2\|Selector3~92 3 COMB LC7_C14 1 " "Info: 3: + IC(1.900 ns) + CELL(1.400 ns) = 7.000 ns; Loc. = LC7_C14; Fanout = 1; COMB Node = 'sd_top:sd_top1\|sd_state:u2\|Selector3~92'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.300 ns" { sd_top:sd_top1|sd_state:u2|Selector2~111 sd_top:sd_top1|sd_state:u2|Selector3~92 } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 9.000 ns sd_top:sd_top1\|sd_state:u2\|Selector3~93 4 COMB LC8_C14 1 " "Info: 4: + IC(0.600 ns) + CELL(1.400 ns) = 9.000 ns; Loc. = LC8_C14; Fanout = 1; COMB Node = 'sd_top:sd_top1\|sd_state:u2\|Selector3~93'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { sd_top:sd_top1|sd_state:u2|Selector3~92 sd_top:sd_top1|sd_state:u2|Selector3~93 } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.900 ns) 10.500 ns sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[1\] 5 REG LC5_C14 26 " "Info: 5: + IC(0.600 ns) + CELL(0.900 ns) = 10.500 ns; Loc. = LC5_C14; Fanout = 26; REG Node = 'sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.500 ns" { sd_top:sd_top1|sd_state:u2|Selector3~93 sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.600 ns ( 53.33 % ) " "Info: Total cell delay = 5.600 ns ( 53.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.900 ns ( 46.67 % ) " "Info: Total interconnect delay = 4.900 ns ( 46.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.500 ns" { sd_top:sd_top1|sd_cnfg:u1|fresh_req sd_top:sd_top1|sd_state:u2|Selector2~111 sd_top:sd_top1|sd_state:u2|Selector3~92 sd_top:sd_top1|sd_state:u2|Selector3~93 sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.500 ns" { sd_top:sd_top1|sd_cnfg:u1|fresh_req sd_top:sd_top1|sd_state:u2|Selector2~111 sd_top:sd_top1|sd_state:u2|Selector3~92 sd_top:sd_top1|sd_state:u2|Selector3~93 sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } { 0.000ns 1.800ns 1.900ns 0.600ns 0.600ns } { 0.000ns 1.900ns 1.400ns 1.400ns 0.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_55 82 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_55; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[1\] 2 REG LC5_C14 26 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_C14; Fanout = 26; REG Node = 'sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_55 82 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_55; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns sd_top:sd_top1\|sd_cnfg:u1\|fresh_req 2 REG LC5_C15 4 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC5_C15; Fanout = 4; REG Node = 'sd_top:sd_top1\|sd_cnfg:u1\|fresh_req'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clk sd_top:sd_top1|sd_cnfg:u1|fresh_req } "NODE_NAME" } } { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_cnfg:u1|fresh_req } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_cnfg:u1|fresh_req } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_cnfg:u1|fresh_req } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_cnfg:u1|fresh_req } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "sd_cnfg.v" "" { Text "D:/newsdram/sd_cnfg.v" 25 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.500 ns" { sd_top:sd_top1|sd_cnfg:u1|fresh_req sd_top:sd_top1|sd_state:u2|Selector2~111 sd_top:sd_top1|sd_state:u2|Selector3~92 sd_top:sd_top1|sd_state:u2|Selector3~93 sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.500 ns" { sd_top:sd_top1|sd_cnfg:u1|fresh_req sd_top:sd_top1|sd_state:u2|Selector2~111 sd_top:sd_top1|sd_state:u2|Selector3~92 sd_top:sd_top1|sd_state:u2|Selector3~93 sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } { 0.000ns 1.800ns 1.900ns 0.600ns 0.600ns } { 0.000ns 1.900ns 1.400ns 1.400ns 0.900ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[1] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_cnfg:u1|fresh_req } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_cnfg:u1|fresh_req } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[0\] ch_req clk 8.800 ns register " "Info: tsu for register \"sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[0\]\" (data pin = \"ch_req\", clock pin = \"clk\") is 8.800 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.400 ns + Longest pin register " "Info: + Longest pin to register delay is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns ch_req 1 PIN PIN_124 2 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_124; Fanout = 2; PIN Node = 'ch_req'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ch_req } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.900 ns) 5.400 ns sd_top:sd_top1\|sd_state:u2\|Selector2~110 2 COMB LC1_C16 2 " "Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC1_C16; Fanout = 2; COMB Node = 'sd_top:sd_top1\|sd_state:u2\|Selector2~110'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { ch_req sd_top:sd_top1|sd_state:u2|Selector2~110 } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.800 ns) + CELL(0.900 ns) 8.100 ns sd_top:sd_top1\|sd_state:u2\|Selector4~555 3 COMB LC5_C17 1 " "Info: 3: + IC(1.800 ns) + CELL(0.900 ns) = 8.100 ns; Loc. = LC5_C17; Fanout = 1; COMB Node = 'sd_top:sd_top1\|sd_state:u2\|Selector4~555'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.700 ns" { sd_top:sd_top1|sd_state:u2|Selector2~110 sd_top:sd_top1|sd_state:u2|Selector4~555 } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.300 ns) 9.400 ns sd_top:sd_top1\|sd_state:u2\|Selector4~551 4 COMB LC6_C17 1 " "Info: 4: + IC(0.000 ns) + CELL(1.300 ns) = 9.400 ns; Loc. = LC6_C17; Fanout = 1; COMB Node = 'sd_top:sd_top1\|sd_state:u2\|Selector4~551'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.300 ns" { sd_top:sd_top1|sd_state:u2|Selector4~555 sd_top:sd_top1|sd_state:u2|Selector4~551 } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 64 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(1.400 ns) 11.400 ns sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[0\] 5 REG LC7_C17 13 " "Info: 5: + IC(0.600 ns) + CELL(1.400 ns) = 11.400 ns; Loc. = LC7_C17; Fanout = 13; REG Node = 'sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { sd_top:sd_top1|sd_state:u2|Selector4~551 sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.400 ns ( 64.91 % ) " "Info: Total cell delay = 7.400 ns ( 64.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns ( 35.09 % ) " "Info: Total interconnect delay = 4.000 ns ( 35.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.400 ns" { ch_req sd_top:sd_top1|sd_state:u2|Selector2~110 sd_top:sd_top1|sd_state:u2|Selector4~555 sd_top:sd_top1|sd_state:u2|Selector4~551 sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.400 ns" { ch_req ch_req~out sd_top:sd_top1|sd_state:u2|Selector2~110 sd_top:sd_top1|sd_state:u2|Selector4~555 sd_top:sd_top1|sd_state:u2|Selector4~551 sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } { 0.000ns 0.000ns 1.600ns 1.800ns 0.000ns 0.600ns } { 0.000ns 1.900ns 1.900ns 0.900ns 1.300ns 1.400ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_55 82 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_55; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[0\] 2 REG LC7_C17 13 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC7_C17; Fanout = 13; REG Node = 'sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "11.400 ns" { ch_req sd_top:sd_top1|sd_state:u2|Selector2~110 sd_top:sd_top1|sd_state:u2|Selector4~555 sd_top:sd_top1|sd_state:u2|Selector4~551 sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "11.400 ns" { ch_req ch_req~out sd_top:sd_top1|sd_state:u2|Selector2~110 sd_top:sd_top1|sd_state:u2|Selector4~555 sd_top:sd_top1|sd_state:u2|Selector4~551 sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } { 0.000ns 0.000ns 1.600ns 1.800ns 0.000ns 0.600ns } { 0.000ns 1.900ns 1.900ns 0.900ns 1.300ns 1.400ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[0] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dp_rden sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[2\] 12.900 ns register " "Info: tco from clock \"clk\" to destination pin \"dp_rden\" through register \"sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[2\]\" is 12.900 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.900 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns clk 1 CLK PIN_55 82 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_55; Fanout = 82; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[2\] 2 REG LC1_C17 22 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_C17; Fanout = 22; REG Node = 'sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.000 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[2] } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns ( 48.72 % ) " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns ( 51.28 % ) " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.900 ns + " "Info: + Micro clock to output delay of source is 0.900 ns" {  } { { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.100 ns + Longest register pin " "Info: + Longest register to pin delay is 8.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[2\] 1 REG LC1_C17 22 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_C17; Fanout = 22; REG Node = 'sd_top:sd_top1\|sd_state:u2\|sdram_cycle\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sd_top:sd_top1|sd_state:u2|sdram_cycle[2] } "NODE_NAME" } } { "sd_state.v" "" { Text "D:/newsdram/sd_state.v" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(1.400 ns) 3.500 ns rw_sd_mach:u1\|dp_rden 2 COMB LC5_C21 16 " "Info: 2: + IC(2.100 ns) + CELL(1.400 ns) = 3.500 ns; Loc. = LC5_C21; Fanout = 16; COMB Node = 'rw_sd_mach:u1\|dp_rden'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { sd_top:sd_top1|sd_state:u2|sdram_cycle[2] rw_sd_mach:u1|dp_rden } "NODE_NAME" } } { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.900 ns) 8.100 ns dp_rden 3 PIN PIN_38 0 " "Info: 3: + IC(0.700 ns) + CELL(3.900 ns) = 8.100 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'dp_rden'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { rw_sd_mach:u1|dp_rden dp_rden } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 65.43 % ) " "Info: Total cell delay = 5.300 ns ( 65.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.800 ns ( 34.57 % ) " "Info: Total interconnect delay = 2.800 ns ( 34.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.100 ns" { sd_top:sd_top1|sd_state:u2|sdram_cycle[2] rw_sd_mach:u1|dp_rden dp_rden } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.100 ns" { sd_top:sd_top1|sd_state:u2|sdram_cycle[2] rw_sd_mach:u1|dp_rden dp_rden } { 0.000ns 2.100ns 0.700ns } { 0.000ns 1.400ns 3.900ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.900 ns" { clk sd_top:sd_top1|sd_state:u2|sdram_cycle[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.900 ns" { clk clk~out sd_top:sd_top1|sd_state:u2|sdram_cycle[2] } { 0.000ns 0.000ns 2.000ns } { 0.000ns 1.900ns 0.000ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "8.100 ns" { sd_top:sd_top1|sd_state:u2|sdram_cycle[2] rw_sd_mach:u1|dp_rden dp_rden } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "8.100 ns" { sd_top:sd_top1|sd_state:u2|sdram_cycle[2] rw_sd_mach:u1|dp_rden dp_rden } { 0.000ns 2.100ns 0.700ns } { 0.000ns 1.400ns 3.900ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "ch_rw dp_rden 10.000 ns Longest " "Info: Longest tpd from source pin \"ch_rw\" to destination pin \"dp_rden\" is 10.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns ch_rw 1 PIN PIN_54 1 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_54; Fanout = 1; PIN Node = 'ch_rw'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { ch_rw } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.900 ns) 5.400 ns rw_sd_mach:u1\|dp_rden 2 COMB LC5_C21 16 " "Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC5_C21; Fanout = 16; COMB Node = 'rw_sd_mach:u1\|dp_rden'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.500 ns" { ch_rw rw_sd_mach:u1|dp_rden } "NODE_NAME" } } { "rw_sd_mach.v" "" { Text "D:/newsdram/rw_sd_mach.v" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(3.900 ns) 10.000 ns dp_rden 3 PIN PIN_38 0 " "Info: 3: + IC(0.700 ns) + CELL(3.900 ns) = 10.000 ns; Loc. = PIN_38; Fanout = 0; PIN Node = 'dp_rden'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.600 ns" { rw_sd_mach:u1|dp_rden dp_rden } "NODE_NAME" } } { "sd_if.v" "" { Text "D:/newsdram/sd_if.v" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns ( 77.00 % ) " "Info: Total cell delay = 7.700 ns ( 77.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 23.00 % ) " "Info: Total interconnect delay = 2.300 ns ( 23.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "10.000 ns" { ch_rw rw_sd_mach:u1|dp_rden dp_rden } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "10.000 ns" { ch_rw ch_rw~out rw_sd_mach:u1|dp_rden dp_rden } { 0.000ns 0.000ns 1.600ns 0.700ns } { 0.000ns 1.900ns 1.900ns 3.900ns } } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}