sd_top.sim.rpt

来自「8读8写SDRAM verilog 程序」· RPT 代码 · 共 390 行 · 第 1/5 页

; |sd_top|sd_cnfg:u1|Selector8~139                                                     ; |sd_top|sd_cnfg:u1|Selector8~139                                                                     ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add~620                                                         ; |sd_top|sd_sig:u4|sd_add~620                                                                         ; cascout          ;
; |sd_top|sd_sig:u4|sd_add~581                                                         ; |sd_top|sd_sig:u4|sd_add~581                                                                         ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add~623                                                         ; |sd_top|sd_sig:u4|sd_add~623                                                                         ; cascout          ;
; |sd_top|sd_sig:u4|sd_add~582                                                         ; |sd_top|sd_sig:u4|sd_add~582                                                                         ; data_out0        ;
; |sd_top|sd_cnfg:u1|state.refresh2                                                    ; |sd_top|sd_cnfg:u1|state.refresh2                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector3~105                                                    ; |sd_top|sd_state:u2|Selector3~105                                                                    ; cascout          ;
; |sd_top|sd_state:u2|Selector3~100                                                    ; |sd_top|sd_state:u2|Selector3~100                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector4~393                                                    ; |sd_top|sd_state:u2|Selector4~393                                                                    ; cascout          ;
; |sd_top|sd_state:u2|Selector4~389                                                    ; |sd_top|sd_state:u2|Selector4~389                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|state.nop2                                                        ; |sd_top|sd_cnfg:u1|state.nop2                                                                        ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[6] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[6]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[3]                 ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[3]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[2]                 ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[2]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[1]                 ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[1]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[0]                 ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[0]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|fresh_req~114                                                    ; |sd_top|sd_rfrsh:u3|fresh_req~114                                                                    ; cascout          ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[4]                 ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[4] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[4]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[5]                 ; data_out0        ;
; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|q[5] ; |sd_top|sd_rfrsh:u3|lpm_counter:rfrsh_cntr_rtl_0|alt_counter_f10ke:wysi_counter|counter_cell[5]~COUT ; cout             ;
; |sd_top|sd_rfrsh:u3|fresh_req~109                                                    ; |sd_top|sd_rfrsh:u3|fresh_req~109                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|state.refresh1                                                    ; |sd_top|sd_cnfg:u1|state.refresh1                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|Selector9~104                                                     ; |sd_top|sd_cnfg:u1|Selector9~104                                                                     ; cascout          ;
; |sd_top|sd_cnfg:u1|Selector9~100                                                     ; |sd_top|sd_cnfg:u1|Selector9~100                                                                     ; data_out0        ;
; |sd_top|clk                                                                          ; |sd_top|clk                                                                                          ; dataout          ;
; |sd_top|rs_ready                                                                     ; |sd_top|rs_ready                                                                                     ; dataout          ;
; |sd_top|data_req                                                                     ; |sd_top|data_req                                                                                     ; dataout          ;
; |sd_top|sd_cs0_l                                                                     ; |sd_top|sd_cs0_l                                                                                     ; padio            ;
; |sd_top|sd_ras_l                                                                     ; |sd_top|sd_ras_l                                                                                     ; padio            ;
; |sd_top|sd_cas_l                                                                     ; |sd_top|sd_cas_l                                                                                     ; padio            ;
; |sd_top|sd_we_l                                                                      ; |sd_top|sd_we_l                                                                                      ; padio            ;
; |sd_top|sd_add[4]                                                                    ; |sd_top|sd_add[4]                                                                                    ; padio            ;
; |sd_top|sd_add[5]                                                                    ; |sd_top|sd_add[5]                                                                                    ; padio            ;
; |sd_top|sd_add[6]                                                                    ; |sd_top|sd_add[6]                                                                                    ; padio            ;
; |sd_top|sd_add[8]                                                                    ; |sd_top|sd_add[8]                                                                                    ; padio            ;
; |sd_top|sd_add[9]                                                                    ; |sd_top|sd_add[9]                                                                                    ; padio            ;
; |sd_top|sd_add[10]                                                                   ; |sd_top|sd_add[10]                                                                                   ; padio            ;
; |sd_top|data_cycle                                                                   ; |sd_top|data_cycle                                                                                   ; padio            ;
; |sd_top|state_cntr[0]                                                                ; |sd_top|state_cntr[0]                                                                                ; padio            ;
; |sd_top|state_cntr[1]                                                                ; |sd_top|state_cntr[1]                                                                                ; padio            ;
; |sd_top|state_cntr[2]                                                                ; |sd_top|state_cntr[2]                                                                                ; padio            ;
; |sd_top|state_cntr[3]                                                                ; |sd_top|state_cntr[3]                                                                                ; padio            ;
; |sd_top|state_cntr[4]                                                                ; |sd_top|state_cntr[4]                                                                                ; padio            ;
; |sd_top|state_cntr[5]                                                                ; |sd_top|state_cntr[5]                                                                                ; padio            ;
; |sd_top|state_cntr[6]                                                                ; |sd_top|state_cntr[6]                                                                                ; padio            ;
; |sd_top|state_cntr[7]                                                                ; |sd_top|state_cntr[7]                                                                                ; padio            ;
; |sd_top|sd_state:u2|sdram_cycle[3]~$wirecell                                         ; |sd_top|sd_state:u2|sdram_cycle[3]~$wirecell                                                         ; data_out0        ;
+--------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                                                                                                                        ;
+---------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                             ; Output Port Name                                                                                     ; Output Port Type ;
+---------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; |sd_top|sd_sig:u4|sd_ba[0]                                                            ; |sd_top|sd_sig:u4|sd_ba[0]                                                                           ; data_out0        ;
; |sd_top|sd_sig:u4|sd_ba[1]                                                            ; |sd_top|sd_sig:u4|sd_ba[1]                                                                           ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[0]                                                           ; |sd_top|sd_sig:u4|sd_add[0]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[1]                                                           ; |sd_top|sd_sig:u4|sd_add[1]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[2]                                                           ; |sd_top|sd_sig:u4|sd_add[2]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[3]                                                           ; |sd_top|sd_sig:u4|sd_add[3]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[7]                                                           ; |sd_top|sd_sig:u4|sd_add[7]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[0]                                                           ; |sd_top|sd_sig:u4|sd_dqm[0]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[1]                                                           ; |sd_top|sd_sig:u4|sd_dqm[1]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[2]                                                           ; |sd_top|sd_sig:u4|sd_dqm[2]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[3]                                                           ; |sd_top|sd_sig:u4|sd_dqm[3]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[4]                                                           ; |sd_top|sd_sig:u4|sd_dqm[4]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[5]                                                           ; |sd_top|sd_sig:u4|sd_dqm[5]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[6]                                                           ; |sd_top|sd_sig:u4|sd_dqm[6]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[7]                                                           ; |sd_top|sd_sig:u4|sd_dqm[7]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[8]                                                           ; |sd_top|sd_sig:u4|sd_dqm[8]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_dqm[9]                                                           ; |sd_top|sd_sig:u4|sd_dqm[9]                                                                          ; data_out0        ;