sd_top.sim.rpt

来自「8读8写SDRAM verilog 程序」· RPT 代码 · 共 390 行 · 第 1/5 页

; Glitch Filtering                                                                           ; Off        ; Off           ;
+--------------------------------------------------------------------------------------------+------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      45.58 % ;
; Total nodes checked                                 ; 211          ;
; Total output ports checked                          ; 215          ;
; Total output ports with complete 1/0-value coverage ; 98           ;
; Total output ports with no 1/0-value coverage       ; 103          ;
; Total output ports with no 1-value coverage         ; 105          ;
; Total output ports with no 0-value coverage         ; 115          ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                                                                                                                    ;
+--------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; Node Name                                                                            ; Output Port Name                                                                                     ; Output Port Type ;
+--------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------+------------------+
; |sd_top|sd_sig:u4|sd_cs0_l                                                           ; |sd_top|sd_sig:u4|sd_cs0_l                                                                           ; data_out0        ;
; |sd_top|sd_sig:u4|sd_ras_l                                                           ; |sd_top|sd_sig:u4|sd_ras_l                                                                           ; data_out0        ;
; |sd_top|sd_sig:u4|sd_cas_l                                                           ; |sd_top|sd_sig:u4|sd_cas_l                                                                           ; data_out0        ;
; |sd_top|sd_sig:u4|sd_we_l                                                            ; |sd_top|sd_sig:u4|sd_we_l                                                                            ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[4]                                                          ; |sd_top|sd_sig:u4|sd_add[4]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[5]                                                          ; |sd_top|sd_sig:u4|sd_add[5]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[6]                                                          ; |sd_top|sd_sig:u4|sd_add[6]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[8]                                                          ; |sd_top|sd_sig:u4|sd_add[8]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[9]                                                          ; |sd_top|sd_sig:u4|sd_add[9]                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add[10]                                                         ; |sd_top|sd_sig:u4|sd_add[10]                                                                         ; data_out0        ;
; |sd_top|sd_state:u2|sdram_cycle[2]                                                   ; |sd_top|sd_state:u2|sdram_cycle[2]                                                                   ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[0]                                                      ; |sd_top|sd_sig:u4|state_cntr[0]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[1]                                                      ; |sd_top|sd_sig:u4|state_cntr[1]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[2]                                                      ; |sd_top|sd_sig:u4|state_cntr[2]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[3]                                                      ; |sd_top|sd_sig:u4|state_cntr[3]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[4]                                                      ; |sd_top|sd_sig:u4|state_cntr[4]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[5]                                                      ; |sd_top|sd_sig:u4|state_cntr[5]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[6]                                                      ; |sd_top|sd_sig:u4|state_cntr[6]                                                                      ; data_out0        ;
; |sd_top|sd_sig:u4|state_cntr[7]                                                      ; |sd_top|sd_sig:u4|state_cntr[7]                                                                      ; data_out0        ;
; |sd_top|sd_state:u2|sdram_cycle[4]                                                   ; |sd_top|sd_state:u2|sdram_cycle[4]                                                                   ; data_out0        ;
; |sd_top|sd_sig:u4|sd_ba~128                                                          ; |sd_top|sd_sig:u4|sd_ba~128                                                                          ; data_out0        ;
; |sd_top|sd_state:u2|sdram_cycle[1]                                                   ; |sd_top|sd_state:u2|sdram_cycle[1]                                                                   ; data_out0        ;
; |sd_top|sd_state:u2|sdram_cycle[3]                                                   ; |sd_top|sd_state:u2|sdram_cycle[3]                                                                   ; data_out0        ;
; |sd_top|sd_state:u2|Selector2~101                                                    ; |sd_top|sd_state:u2|Selector2~101                                                                    ; data_out0        ;
; |sd_top|sd_sig:u4|always5~11                                                         ; |sd_top|sd_sig:u4|always5~11                                                                         ; data_out0        ;
; |sd_top|sd_sig:u4|always5~1                                                          ; |sd_top|sd_sig:u4|always5~1                                                                          ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add~523                                                         ; |sd_top|sd_sig:u4|sd_add~523                                                                         ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add~525                                                         ; |sd_top|sd_sig:u4|sd_add~525                                                                         ; data_out0        ;
; |sd_top|sd_sig:u4|sd_add~527                                                         ; |sd_top|sd_sig:u4|sd_add~527                                                                         ; data_out0        ;
; |sd_top|sd_state:u2|sdram_cycle[0]                                                   ; |sd_top|sd_state:u2|sdram_cycle[0]                                                                   ; data_out0        ;
; |sd_top|sd_state:u2|Selector2~102                                                    ; |sd_top|sd_state:u2|Selector2~102                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector2~103                                                    ; |sd_top|sd_state:u2|Selector2~103                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|load_req                                                          ; |sd_top|sd_cnfg:u1|load_req                                                                          ; data_out0        ;
; |sd_top|sd_cnfg:u1|fresh_req                                                         ; |sd_top|sd_cnfg:u1|fresh_req                                                                         ; data_out0        ;
; |sd_top|sd_state:u2|Selector2~104                                                    ; |sd_top|sd_state:u2|Selector2~104                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|charge_req                                                        ; |sd_top|sd_cnfg:u1|charge_req                                                                        ; data_out0        ;
; |sd_top|sd_state:u2|Selector3~92                                                     ; |sd_top|sd_state:u2|Selector3~92                                                                     ; data_out0        ;
; |sd_top|sd_state:u2|Selector0~130                                                    ; |sd_top|sd_state:u2|Selector0~130                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector0~131                                                    ; |sd_top|sd_state:u2|Selector0~131                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector0~132                                                    ; |sd_top|sd_state:u2|Selector0~132                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector3~94                                                     ; |sd_top|sd_state:u2|Selector3~94                                                                     ; data_out0        ;
; |sd_top|sd_state:u2|Selector1~145                                                    ; |sd_top|sd_state:u2|Selector1~145                                                                    ; data_out0        ;
; |sd_top|sd_state:u2|Selector4~381                                                    ; |sd_top|sd_state:u2|Selector4~381                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|state.load_mode                                                   ; |sd_top|sd_cnfg:u1|state.load_mode                                                                   ; data_out0        ;
; |sd_top|sd_rfrsh:u3|fresh_req~101                                                    ; |sd_top|sd_rfrsh:u3|fresh_req~101                                                                    ; data_out0        ;
; |sd_top|sd_cnfg:u1|state.precharge                                                   ; |sd_top|sd_cnfg:u1|state.precharge                                                                   ; data_out0        ;