sd_sig.v

8读8写SDRAM verilog 程序

`timescale 1 ns /  100 ps
//---------------------------------------------------------------------
// mode register defines
// write mode set to single or programmed burst length -- mode bit[9]
`define prog_brst   0
`define single      1
// cas latency set to 2 or 3 -- mode bits[6:4]
`define cas_lat_2   3'b010
`define cas_lat_3   3'b011

// burst type sequential or interleaved -- mode bit[3]
`define seq         1'b0
`define int         1'b1

// burst length -- mode bits[2:0]
`define brst1       3'b000                 // 1
`define brst2       3'b001                 // 2
`define brst4       3'b010                 // 4
`define brst8       3'b011                 // 8
`define brstf       3'b111                 // full page

module sd_sig(  
                rst_l,                 
                clk,

				add,
                wr_l,
                byte_en,


				idle_cycle,		
				load_cycle,	
				data_cycle, 		
				fresh_cycle, 		
				charge_cycle,
				
				state_cntr,

                sd_add,
                sd_ba,
                sd_cs0_l,
                sd_ras_l,
                sd_cas_l,
                sd_we_l,
                sd_cke,
                sd_dqm,

				rs_ready
				);
//---------------------------------------------------------------------
// inputs
input           rst_l;           
input           clk;

input  [24:0]	add;
input           wr_l;
input  [15:0]   byte_en;


input			idle_cycle;
input			load_cycle;	
input			data_cycle;		
input			fresh_cycle;	
input			charge_cycle;

output[7:0]		state_cntr;

input			rs_ready;
//---------------------------------------------------------------------
// outputs          
output [11:0]   sd_add;
output [1:0]    sd_ba;
output          sd_cs0_l;
output          sd_ras_l;
output          sd_cas_l;
output          sd_we_l;
output          sd_cke;
output [15:0]   sd_dqm;//dqm length modified to 4

				
//---------------------------------------------------------------------
// registers

reg    [11:0]   sd_add;
reg    [1:0]    sd_ba;
reg             sd_cs0_l;
reg             sd_ras_l;
reg             sd_cas_l;
reg             sd_we_l;
reg             sd_cke;
reg    [15:0]   sd_dqm;//dqm length modified to 4
reg             ack_l;
reg             term_lcatch;
reg             term_ldly;
//---------------------------------------------------------------------
// sdram mode register assignment
// change values to whatever you need
wire[11:0]   sdram_mode_reg;
//assign	sdram_mode_reg=12'd0;
assign	sdram_mode_reg[11]		=1'b0;
assign 	sdram_mode_reg[10] 		 = 1'b0;        // reserved
assign 	sdram_mode_reg[9]     = `single;  // write mode
assign 	sdram_mode_reg[8:7]   = 2'b0;        // reserved
assign 	sdram_mode_reg[6:4]   = `cas_lat_3;  // cas latency 2 clocks
assign 	sdram_mode_reg[3]     = `seq;        // sequential access
assign 	sdram_mode_reg[2:0]   = `brst1;      // burst of 8
// equations
always @(posedge clk or negedge rst_l)
   	if (!rst_l)
        sd_add <=  #1  12'h400;                     	// precharge  A10 == 1
           //A10 is sampled during a PRECHARGE command to
           //determine if all banks are to be precharged (A10 HIGH) or bank selected by
           //BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD
           //MODE REGISTER command
   	else if (load_cycle && state_cntr[0])			//load
        sd_add <=  #1  sdram_mode_reg;              
   	else if (data_cycle && state_cntr[0])  			//ras time  
        sd_add <=  #1  {1'b0,add[22:12]};   
   	else if (data_cycle && rs_ready)  			//cas time		add[11:4]是列地址
        sd_add <=  #1  {4'h0,add[11:4]};						
   	else if(charge_cycle && state_cntr[0])			//prechage cycle
		sd_add <=  #1  12'h400; 
	else if(fresh_cycle && state_cntr[0])			//fresh
		sd_add <=  #1 12'h400;
   	else
        sd_add <=  #1  12'h400;
// bank addresses
always @(posedge clk or negedge rst_l)
   	if (!rst_l)
        sd_ba <=  #1  2'b00;							// precharge
   	else if (load_cycle && state_cntr[0])			//load
		sd_ba <=  #1  2'd0;	
   	else if (data_cycle && state_cntr[0])  			// ras time  
        sd_ba <=  #1  add[24:23];             
   	else if (data_cycle && rs_ready)  			// cas time
        sd_ba <=  #1  add[24:23];
   	else if(charge_cycle && state_cntr[0])			//prechage cycle
		sd_ba <=  #1  add[24:23];
	else if(fresh_cycle && state_cntr[0])		
		sd_ba<=  #1  2'b00;
   	else											
        sd_ba <=  #1  2'b00;

// chip select 0
always @(posedge clk or negedge rst_l)  //对于sdram片选信号,在各个周期都应有