sd_if.map.rpt

8读8写SDRAM verilog 程序

Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Thu Jan 24 21:37:56 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off sd_if -c sd_if
Warning: Using design file sd_if.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sd_if
Info: Elaborating entity "sd_if" for the top level hierarchy
Warning: Using design file rw_sd_mach.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: rw_sd_mach
Info: Elaborating entity "rw_sd_mach" for hierarchy "rw_sd_mach:u1"
Warning: Using design file sd_top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sd_top
Info: Elaborating entity "sd_top" for hierarchy "sd_top:sd_top1"
Warning: Using design file sd_cnfg.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sd_cnfg
Info: Elaborating entity "sd_cnfg" for hierarchy "sd_top:sd_top1|sd_cnfg:u1"
Warning: Using design file sd_state.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sd_state
Info: Elaborating entity "sd_state" for hierarchy "sd_top:sd_top1|sd_state:u2"
Info (10264): Verilog HDL Case Statement information at sd_state.v(64): all case item expressions in this case statement are onehot
Warning: Using design file sd_rfrsh.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sd_rfrsh
Info: Elaborating entity "sd_rfrsh" for hierarchy "sd_top:sd_top1|sd_rfrsh:u3"
Warning: Using design file sd_sig.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
    Info: Found entity 1: sd_sig
Info: Elaborating entity "sd_sig" for hierarchy "sd_top:sd_top1|sd_sig:u4"
Warning: Reduced register "rw_sd_mach:u1|op_en" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_num[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_active" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|rs_ready" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|rs_ready_delay[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[12]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[10]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[9]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[7]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[6]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[5]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[0]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|rs_ready_delay[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "sd_top:sd_top1|sd_sig:u4|sd_dqm[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|rs_ready_delay[2]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|rs_ready_delay[3]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|rs_ready_delay[4]" with stuck data_in port to stuck value GND
Warning: Reduced register "rw_sd_mach:u1|op_over" with stuck data_in port to stuck value GND
Info: State machine "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state" contains 7 states
Info: Selected Auto state machine encoding method for state machine "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state"
Info: Encoding result for state machine "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state"
    Info: Completed encoding using 7 state bits
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.precharge"
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.refresh1"
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.nop2"
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.refresh2"
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.load_mode"
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.idle"
        Info: Encoded state bit "sd_top:sd_top1|sd_cnfg:u1|state.all_done"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.idle" uses code string "0000000"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.load_mode" uses code string "0000110"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.refresh2" uses code string "0001010"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.nop2" uses code string "0010010"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.refresh1" uses code string "0100010"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.precharge" uses code string "1000010"
    Info: State "|sd_if|sd_top:sd_top1|sd_cnfg:u1|state.all_done" uses code string "0000011"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ch_ack" stuck at GND
    Warning: Pin "dp_wren" stuck at GND
    Warning: Pin "sd_dqm[0]" stuck at GND
    Warning: Pin "sd_dqm[1]" stuck at GND
    Warning: Pin "sd_dqm[2]" stuck at GND
    Warning: Pin "sd_dqm[3]" stuck at GND
    Warning: Pin "sd_dqm[4]" stuck at GND
    Warning: Pin "sd_dqm[5]" stuck at GND
    Warning: Pin "sd_dqm[6]" stuck at GND
    Warning: Pin "sd_dqm[7]" stuck at GND
    Warning: Pin "sd_dqm[8]" stuck at GND
    Warning: Pin "sd_dqm[9]" stuck at GND
    Warning: Pin "sd_dqm[10]" stuck at GND
    Warning: Pin "sd_dqm[11]" stuck at GND
    Warning: Pin "sd_dqm[12]" stuck at GND
    Warning: Pin "sd_dqm[13]" stuck at GND
    Warning: Pin "sd_dqm[14]" stuck at GND
    Warning: Pin "sd_dqm[15]" stuck at GND
    Warning: Pin "rs_ready" stuck at GND
Info: Registers with preset signals will power-up high
Warning: Design contains 32 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "ch_addr[0]"
    Warning: No output dependent on input pin "ch_addr[1]"
    Warning: No output dependent on input pin "ch_addr[2]"
    Warning: No output dependent on input pin "ch_addr[3]"
    Warning: No output dependent on input pin "ch_addr[4]"
    Warning: No output dependent on input pin "ch_addr[5]"
    Warning: No output dependent on input pin "ch_addr[6]"
    Warning: No output dependent on input pin "ch_addr[7]"
    Warning: No output dependent on input pin "ch_num[0]"
    Warning: No output dependent on input pin "ch_num[1]"
    Warning: No output dependent on input pin "ch_num[2]"
    Warning: No output dependent on input pin "ch_num[3]"
    Warning: No output dependent on input pin "ch_num[4]"
    Warning: No output dependent on input pin "ch_num[5]"
    Warning: No output dependent on input pin "ch_num[6]"
    Warning: No output dependent on input pin "ch_num[7]"
    Warning: No output dependent on input pin "ch_dqm[0]"
    Warning: No output dependent on input pin "ch_dqm[1]"
    Warning: No output dependent on input pin "ch_dqm[2]"
    Warning: No output dependent on input pin "ch_dqm[3]"
    Warning: No output dependent on input pin "ch_dqm[4]"
    Warning: No output dependent on input pin "ch_dqm[5]"
    Warning: No output dependent on input pin "ch_dqm[6]"
    Warning: No output dependent on input pin "ch_dqm[7]"
    Warning: No output dependent on input pin "ch_dqm[8]"
    Warning: No output dependent on input pin "ch_dqm[9]"
    Warning: No output dependent on input pin "ch_dqm[10]"
    Warning: No output dependent on input pin "ch_dqm[11]"
    Warning: No output dependent on input pin "ch_dqm[12]"
    Warning: No output dependent on input pin "ch_dqm[13]"
    Warning: No output dependent on input pin "ch_dqm[14]"
    Warning: No output dependent on input pin "ch_dqm[15]"
Info: Implemented 206 device resources after synthesis - the final resource count might be different
    Info: Implemented 50 input pins
    Info: Implemented 47 output pins
    Info: Implemented 109 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 92 warnings
    Info: Processing ended: Thu Jan 24 21:37:57 2008
    Info: Elapsed time: 00:00:01