sd_top.hif

8读8写SDRAM verilog 程序

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	sd_cnfg.v
	{
		sd_cnfg [idle=0,precharge=1,nop1=10,refresh1=11,nop2=100,refresh2=101,nop3=110,load_mode=111,all_done=1000] []
		{
			2 [idle=0,precharge=1,nop1=10,refresh1=11,nop2=100,refresh2=101,nop3=110,load_mode=111,all_done=1000] [];
		}
	}
	sd_state.v
	{
		sd_state [idle=1,load=10,data=100,fresh=1000,charge=10000,cas_time=11] []
		{
			1 [idle=1,load=10,data=100,fresh=1000,charge=10000,cas_time=11] [];
		}
	}
	sd_rfrsh.v
	{
		sd_rfrsh [cnt_110=1738,cnt_80=1264,cnt_66=1053,cnt_50=790,cnt_40=632,cnt_33=526,count=1053] []
		{
			3 [cnt_110=1738,cnt_80=1264,cnt_66=1053,cnt_50=790,cnt_40=632,cnt_33=526,count=1053] [];
		}
	}
	sd_sig.v
	{
		sd_sig [] []
		{
			8 [] [];
		}
	}
	lpm_add_sub.tdf
	{
		lpm_add_sub [USE_LPM_FOR_AHDL_OPERATORS,LPM_WIDTH,LPM_REPRESENTATION=SIGNED,LPM_DIRECTION=DEFAULT,ONE_INPUT_IS_CONSTANT=NO,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY,STYLE] [aglobal.inc,altshift.inc,bypassff.inc,look_add.inc,addcore.inc,lpm_add_sub.inc]
		{
			4 [USE_LPM_FOR_AHDL_OPERATORS=OFF,LPM_WIDTH=11,LPM_REPRESENTATION=UNSIGNED,LPM_DIRECTION=ADD,ONE_INPUT_IS_CONSTANT=YES,LPM_PIPELINE=0,MAXIMIZE_SPEED=5,OPTIMIZE_FOR_SPEED=5,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K,STYLE=NORMAL] [DATAA10,DATAA9,DATAA8,DATAA7,DATAA6,DATAA5,DATAA4,DATAA3,DATAA2,DATAA1,DATAA0,DATAB10,DATAB9,DATAB8,DATAB7,DATAB6,DATAB5,DATAB4,DATAB3,DATAB2,DATAB1,DATAB0,RESULT0,RESULT1,RESULT2,RESULT3,RESULT4,RESULT5,RESULT6,RESULT7,RESULT8,RESULT9,RESULT10];
		}
	}
	addcore.tdf
	{
		addcore [USE_LPM_FOR_AHDL_OPERATORS,width,CONSTANT_CIN,CARRY_CHAIN,CARRY_CHAIN_LENGTH,DEVICE_FAMILY] [aglobal.inc,addcore.inc]
		{
			5 [USE_LPM_FOR_AHDL_OPERATORS=OFF,width=11,CONSTANT_CIN=1,CARRY_CHAIN=IGNORE,CARRY_CHAIN_LENGTH=32,DEVICE_FAMILY=FLEX10K] [cin,datab0,datab1,datab2,datab3,datab4,datab5,datab6,datab7,datab8,datab9,datab10,dataa0,dataa1,dataa2,dataa3,dataa4,dataa5,dataa6,dataa7,dataa8,dataa9,dataa10,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10];
		}
	}
	altshift.tdf
	{
		altshift [USE_LPM_FOR_AHDL_OPERATORS,WIDTH=4,DEPTH=0] []
		{
			6 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=11,DEPTH=0] [data0,data1,data2,data3,data4,data5,data6,data7,data8,data9,data10,result0,result1,result2,result3,result4,result5,result6,result7,result8,result9,result10];
			7 [USE_LPM_FOR_AHDL_OPERATORS=OFF,WIDTH=1,DEPTH=0] [data0,result0];
		}
	}
	sd_top.v
	{
		sd_top [] [sd_cnfg.v,sd_state.v,sd_rfrsh.v,sd_sig.v]
		{
			0 [] [];
		}
	}
}
TREE
{
	sd_top::(0,0):(0): sd_top.v
	{
		sd_state:1:(87,0):(95,u2): sd_state.v;
		sd_cnfg:2:(73,0):(96,u1): sd_cnfg.v;
		sd_rfrsh:3:(104,0):(97,u3): sd_rfrsh.v
		{
			lpm_add_sub:4:(36,0):(73): lpm_add_sub.tdf
			{
				addcore:5:(212,4):(67,adder): addcore.tdf;
				altshift:6:(222,2):(107,result_ext_latency_ffs): altshift.tdf;
				altshift:7:(224,2):(135,carry_ext_latency_ffs): altshift.tdf;
				altshift:7:(226,2):(143,oflow_ext_latency_ffs): altshift.tdf;
			}
		}
		sd_sig:8:(111,0):(98,u4): sd_sig.v;
	}
}