fifo2_tb.v

verilog开发的FIFO

module FIFO2_TB;
reg clk;
reg rstp;
reg [15:0] din;
reg readp;
reg writep;

wire [15:0] dout;
wire emptyp;
wire fullp;

reg  [15:0] value;

FIFO2 FIFO2_T(
              .clk(clk),
              .rstp(rstp),
              .din(din),
              .readp(readp),
              .writep(writep),
              .dout(dout),
              .emptyp(emptyp),
              .fullp(fullp)
              );
              
task read_word;
  begin
    @ (negedge clk);
      readp =1;
    @ (posedge clk) 
      #5;
      $display ("Read %Oh from FIFO",dout);
      readp =0;
   end
endtask

task write_word;
input [15:0] value;
begin
  @(negedge clk);
    din=value;
    writep=1;
  @(posedge clk);
    $display ("Write %Oh to FIFO",din);
    #5;
    din=16'hzzzz;
    writep=0;
end
endtask

task read_write_word;
input [15:0] value;
  begin
    @ (negedge clk);
      readp =1;
      din=value;
      writep=1;
    @(posedge clk);
       #5;
       readp =0;
       din=16'hzzzz;
       writep=0;
  end
endtask

initial 
  begin
   clk=0;
   forever  
     begin
       #10 clk=1;
       #10 clk=0;
     end
   end
   
   
initial
  begin
    $shm_open("./fifo.shm");
    $shm_probe(FIFO2_TB,"AS");
    
    test1;
    //test2;
    
    $shm_close;
    $finish;
  end
  
  
task test1;
  begin
    din=16'hzzzz;
    writep=0;
    readp=0;
    
    rstp=1;
    #50;
    rstp=0;
    #50;
    
    write_word(16'h1111);
    write_word(16'h2222);
    write_word(16'h3333);
    
    read_word;
    read_word;
    
    write_word(16'h4444);
    
    repeat(6)
      begin
        read_word;
      end
      
    write_word(16'h0001);
    write_word(16'h0002);
    write_word(16'h0003);
    write_word(16'h0004);
    write_word(16'h0005);
    write_word(16'h0006);
    write_word(16'h0007);
    write_word(16'h0008);
    
    repeat(6)
      begin
        read_word;
      end
      
      // write_word(16'h0008);
       
    repeat(6)
      begin 
       read_write_word($random%50);
      end
      
      $display("Done TEST1.");
    end
 endtask

  
  
task test2;
  reg [15:0]  write_counter;
  begin
  
    write_counter=16'h0001;
    din=16'hzzzz;
    writep=0;
    readp=0;
    
    rstp=1;
    #50;
    rstp=0;
    #50;
    
    fork
      begin
        repeat(500)
          begin
            @(negedge clk);
             if(fullp==1'b0)
               begin
                 write_word(write_counter);
                 #5;
                 write_counter = write_counter + 1;
               end
             else
               begin
                 $display("WRITE is waiting..");
               end
                #(50+($random%50));
                $display("Done with WRITER fork..");
                //$finish;
          end
          
       begin
        forever
          begin
            @ (negedge clk)
              if(emptyp==1'b0)
                begin
                  read_word;
                end
               else
                 begin
                   $display("READER is waiting..");
                 end
                 
             #(50+($random%50));
           end
        end
        end
       join
       end
  endtask
    
    
  always @(fullp)
    $display("fullp=%0b",fullp);
    
  always @(emptyp)
    $display("emptyp =%0b",emptyp);
    
  always @(FIFO2_T.head)
    $display("head = %0h",FIFO2_T.head);
    
  always @(FIFO2_T.tail)
    $display("tail =%0h",FIFO2_T.tail);
    
endmodule