ddr2_db_width_72.v

DDR2 的控制器

// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: [e-mail]
// =============================================================================/
//                        FILE DETAILS
// Project          : DDR_MACO SDRAM Controller
// File             : mem_db_width_72.v
// Title            : Module with 72 bit data bus
// Dependencies     : None
// Description      : Instantiates nine mt46v8m16 devices
// =============================================================================
//                        REVISION HISTORY
// Version          : 1.0
// Author           : Sreenidhi Raatni
// Mod. Date        : Aug 8, 2003
// Changes Made     : Initial Creation
//
// =============================================================================

`timescale 1 ps / 1 ps

module ddr2_db_width_72 (
    ddr_dq, 
    ddr_dqs, 
    ddr_dqs_n, 
    ddr_ba, 
    ddr_ad,
    ddr_clk, 
    ddr_clk_n, 
    ddr_cke, 
    ddr_cs_n, 
    ddr_odt, 
    ddr_ras_n, 
    ddr_cas_n, 
    ddr_we_n, 
    ddr_dqm
);

inout  [71:0]           ddr_dq;
inout  [8:0]            ddr_dqs;
inout  [8:0]            ddr_dqs_n;
input  [`BNK_WDTH-1:0]  ddr_ba;
input  [`ROW_WIDTH-1:0] ddr_ad;
input                   ddr_clk;
input                   ddr_clk_n;
input                   ddr_cke;
input  [`CS_WIDTH-1:0]  ddr_cs_n;
input  [`CS_WIDTH-1:0]  ddr_odt;
input                   ddr_ras_n;
input                   ddr_cas_n;
input                   ddr_we_n;
input  [8:0]            ddr_dqm;

genvar i;
genvar j;

generate	
for (j=0; j<`CS_WIDTH; j=j+1) begin : cs	
 for (i=0; i<9; i=i+1)    begin: u
 
 	ddr2 cs_mem0 (
       	    .dq      	(ddr_dq[8*(i+1) - 1:8*(i)]),	
	    .dqs    	(ddr_dqs[i]),
            .dqs_n  	(ddr_dqs_n[i]),
            .dm_rdqs  	(ddr_dqm[i]),                   
            .rdqs_n  	(),	    
	    .addr    	(ddr_ad),
	    .ba      	(ddr_ba),
	    .ck       	(ddr_clk),
	    .ck_n    	(ddr_clk_n),
	    .cke     	(ddr_cke),
	    .cs_n    	(ddr_cs_n[j]),
	    .ras_n   	(ddr_ras_n),
	    .cas_n   	(ddr_cas_n),
	    .we_n    	(ddr_we_n),
	    .odt     	(ddr_odt[j])
	);

end // block: u
end // block: cs
endgenerate

endmodule