ddr_sdram_mem_top.plg

来自「DDR2 的控制器」· PLG 代码 · 共 13 行

@P:  Worst Slack : 1.278
@P:  ddr_sdram_mem_top|pll_266M.k_clk_inferred_clock - Estimated Frequency : 268.7 MHz
@P:  ddr_sdram_mem_top|pll_266M.k_clk_inferred_clock - Requested Frequency : 200.0 MHz
@P:  ddr_sdram_mem_top|pll_266M.k_clk_inferred_clock - Estimated Period : 3.722
@P:  ddr_sdram_mem_top|pll_266M.k_clk_inferred_clock - Requested Period : 5.000
@P:  ddr_sdram_mem_top|pll_266M.k_clk_inferred_clock - Slack : 1.278
@P:  System - Estimated Frequency : 366.6 MHz
@P:  System - Requested Frequency : 200.0 MHz
@P:  System - Estimated Period : 2.728
@P:  System - Requested Period : 5.000
@P:  System - Slack : 2.272
@P:  CPU Time : 0h:00m:02s