ddr_dqs_io.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: ddr_dqs_io.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================
`timescale 1ns/100ps
`include "ddr_sdram_mem_params.v"
module ddr_dqs_io (
    
    rst,
    core_clk,
    // Input signal from the core
    pio_read,
    tri_en,

    // Input signal from the Master DLL
   
    dqsdel  , 

    // output signals to the PIO
    data_valid,
    dqsxfer_clk,
    dqsin_clk,

    // output signals to the core
    dqsout_core,
    prmbdet,
    ddrclkpol,
    ddr_dqs_out,
    dqsi,

    // bi-directional DQS signal at the memory
    bidi
);

//-------------------------------------------------------------------
// Inputs/Outputs 
//-------------------------------------------------------------------
input                          rst;
input                          core_clk;
input   [`DQS_WIDTH-1:0]       pio_read;
input                          tri_en;
input   [`DQS_WIDTH-1:0]       dqsdel;

input   [2*(`DQS_WIDTH)-1:0]   ddr_dqs_out;
output  [`DQS_WIDTH-1:0]       data_valid;
output  [`DQS_WIDTH-1:0]       dqsxfer_clk;
output  [`DQS_WIDTH-1:0]       dqsin_clk;
output  [`DQS_WIDTH-1:0]       dqsout_core;
output  [`DQS_WIDTH-1:0]       prmbdet;
output  [`DQS_WIDTH-1:0]       ddrclkpol;
output  [`DQS_WIDTH-1:0]       dqsi;
inout   [`DQS_WIDTH-1:0]       bidi;

//-------------------------------------------------------------------
// Instintiate DQS 
//-------------------------------------------------------------------
genvar i;  

   generate
     for (i=0; i<(`DQS_WIDTH); i=i+1)   
       begin: u
	  bidi_dqs bidi_dqs (
             .rst           (rst),
             .core_clk      (core_clk),
             .pio_read      (pio_read[i]),
             .tri_en        (tri_en),
             .dqsdel        (dqsdel[i]),
             .data_valid    (data_valid[i]),
             .dqsxfer_clk   (dqsxfer_clk[i]),
             .dqsin_clk     (dqsin_clk[i]),
             .dqsout_core   (dqsout_core[i]),
             .prmbdet       (prmbdet[i]),
             .ddrclkpol     (ddrclkpol[i]),
             .ddr_dqs_out   (ddr_dqs_out[(2*i+1):(2*i)]),
             .dqsi          (dqsi[i]),
             .bidi          (bidi[i])
            );
       end // block: u
   endgenerate


endmodule

module bidi_dqs (
    rst,
    core_clk,
    pio_read,
    tri_en,
    dqsdel,
    data_valid,
    dqsxfer_clk,
    dqsin_clk,
    dqsout_core,
    prmbdet,
    ddrclkpol,
    ddr_dqs_out,
    dqsi,
    bidi
   );

//-------------------------------------------------------------------
// Inputs/Outputs 
//-------------------------------------------------------------------
input          rst;
input          core_clk;
input          pio_read;
input          tri_en;
input          dqsdel;
output         data_valid;
output         dqsxfer_clk;
output         dqsin_clk;
output         dqsout_core;
output         prmbdet;
output         ddrclkpol;
input   [1:0]  ddr_dqs_out;
output         dqsi;
inout          bidi;

// Internal wires
wire       dqsi;
wire       dqsi_tmp;
wire       dqsi_tmp1;
wire       out_to_bb;
wire       tri_en_reg;
wire       data_valid_io;
wire       data_valid_lut;
wire       data_valid;

//-------------------------------------------------------------------
// O/P Flop
//-------------------------------------------------------------------
   ODDRXC U1_ODDRXC (.DA(ddr_dqs_out[1]), .DB(ddr_dqs_out[0]), .RST(rst), 
                  .CLK(core_clk), .Q(out_to_bb)) /* synthesis CLKMODE="SCLK" */;
//-------------------------------------------------------------------
// O/P Tristate Flop
//-------------------------------------------------------------------
  ODDRXC U1_TODDRXC (.DA(tri_en), .DB(tri_en), .RST(rst),
                  .CLK(core_clk), .Q(tri_en_reg)) /* synthesis CLKMODE="SCLK" */;
//-------------------------------------------------------------------
// Instantiate the DQSBUF modules
//-------------------------------------------------------------------
DQSBUFC U1_DQSBUFC (.DQSI(dqsi), .CLK(core_clk), .XCLK(core_clk), .READ(pio_read),
                    .DQSDEL(dqsdel), .DQSO(dqsin_clk),
                    .DDRCLKPOL(ddrclkpol), .DQSC(dqsout_core),
                    .PRMBDET(prmbdet), .DQSXFER(dqsxfer_clk), .DATAVALID(data_valid_io));

`ifdef IO_DATA_VAL 
`else
pio_dvalid_gen U1_pio_dvalid_gen (
   .clk            (core_clk),
   .rst_n          (~rst),
   .prmbdet        (prmbdet),
   .pio_read       (pio_read),
   .dqsi           (dqsi),
   .ddrclkpol      (ddrclkpol),
   .data_valid     (data_valid_lut)
    );
`endif

`ifdef IO_DATA_VAL 
   assign data_valid = data_valid_io;
`else
   assign data_valid = data_valid_lut;
`endif


//-------------------------------------------------------------------
//Parameters for the DQS delay 
//-------------------------------------------------------------------

assign  dqsi_tmp1 = dqsi_tmp;
assign  dqsi = dqsi_tmp1;


//-------------------------------------------------------------------
// Instantiate the BB modules
//-------------------------------------------------------------------
BB U1_BB (.I(out_to_bb), .T(tri_en_reg), .O(dqsi_tmp), .B(bidi));

endmodule