kbar_clk_pll.v

DDR2 的控制器

/* Verilog netlist generated by SCUBA ispLever_v51_Prod_Build (37) */
/* Module Version: 2.0 */
/* C:\ispTOOLS5_1\ispfpga\bin\nt\scuba.exe -w -n kbar_clk_pll -lang verilog -synth synplify -arch ep5a00 -type pll -fin 200 -fclkop 200 -fclkop_tol 0.0 -delay_cntl STATIC -fdel 0 -fb_mode CLKOP -noclkos -pll_rank 2 -noclkok  */
/* Wed Oct 12 14:10:15 2005 */


`timescale 1 ns / 1 ps
`include "ddr_sdram_mem_params.v"
module kbar_clk_pll (CLK, RESET, CLKOP, LOCK);
    input CLK;
    input RESET;
    output CLKOP;
    output LOCK;

    wire CLK_t;

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    
    // synopsys translate_off
    defparam PLLDInst_0.CLKOK_BYPASS = "DISABLED";
    defparam PLLDInst_0.CLKOS_BYPASS = "DISABLED";
    defparam PLLDInst_0.CLKOP_BYPASS = "DISABLED";
    defparam PLLDInst_0.DELAY_CNTL = "STATIC"; 
    defparam PLLDInst_0.PHASE_CNTL = "STATIC"; 
    defparam PLLDInst_0.FDEL = 0;
    defparam PLLDInst_0.DUTY = 8;
    defparam PLLDInst_0.PHASEADJ = "0.0";
    defparam PLLDInst_0.CLKOK_DIV = 2;
    defparam PLLDInst_0.CLKOP_DIV = 4; 
    defparam PLLDInst_0.CLKFB_DIV = 1;
    defparam PLLDInst_0.CLKI_DIV = 1;
     // synopsys translate_on
    
    
    EHXPLLD PLLDInst_0 (.CLKI(CLK_t), .CLKFB(CLKOP_t), .RST(RESET), .RSTK(scuba_vlo), 
        .DDAMODE(scuba_vlo), .DDAIZR(scuba_vlo), .DDAILAG(scuba_vlo), .DDAIDEL0(scuba_vlo), 
        .DDAIDEL1(scuba_vlo), .DDAIDEL2(scuba_vlo), .DPAMODE(scuba_vlo), 
        .DRPAI0(scuba_vlo), .DRPAI1(scuba_vlo), .DRPAI2(scuba_vlo), .DRPAI3(scuba_vlo), 
        .DFPAI0(scuba_vlo), .DFPAI1(scuba_vlo), .DFPAI2(scuba_vlo), .DFPAI3(scuba_vlo), 
        .CLKOP(CLKOP_t), .CLKOS(), .CLKOK(), .LOCK(LOCK), .CLKINTFB())
             /* synthesis CLKOK_BYPASS="DISABLED" */
             /* synthesis CLKOS_BYPASS="DISABLED" */
             /* synthesis CLKOP_BYPASS="DISABLED" */
             /* synthesis PLLCAP="DISABLED" */
             /* synthesis DELAY_CNTL="STATIC" */
             /* synthesis PHASE_CNTL="STATIC" */
             /* synthesis FDEL="0" */
             /* synthesis DUTY="8" */
             /* synthesis PHASEADJ="0.0" */
             /* synthesis FREQUENCY_PIN_CLKOP="200.000" */
             /* synthesis FREQUENCY_PIN_CLKI="200.000" */
             /* synthesis FREQUENCY_PIN_CLKOK="50.000" */
             /* synthesis CLKOK_DIV="2" */
             /* synthesis CLKOP_DIV="4" */
             /* synthesis CLKFB_DIV="1" */
             /* synthesis CLKI_DIV="1" */
             /* synthesis FIN="200.000" */;
    assign CLKOP = CLKOP_t;
    assign CLK_t = CLK;
    // exemplar begin
    // exemplar attribute PLLDInst_0 CLKOK_BYPASS DISABLED
    // exemplar attribute PLLDInst_0 CLKOS_BYPASS DISABLED
    // exemplar attribute PLLDInst_0 CLKOP_BYPASS DISABLED
    // exemplar attribute PLLDInst_0 PLLCAP DISABLED
    // exemplar attribute PLLDInst_0 DELAY_CNTL STATIC
    // exemplar attribute PLLDInst_0 PHASE_CNTL STATIC
    // exemplar attribute PLLDInst_0 FDEL 0
    // exemplar attribute PLLDInst_0 DUTY 8
    // exemplar attribute PLLDInst_0 PHASEADJ 0.0
    // exemplar attribute PLLDInst_0 FREQUENCY_PIN_CLKOP 200.000
    // exemplar attribute PLLDInst_0 FREQUENCY_PIN_CLKI 200.000
    // exemplar attribute PLLDInst_0 FREQUENCY_PIN_CLKOK 50.000
    // exemplar attribute PLLDInst_0 CLKOK_DIV 2
    // exemplar attribute PLLDInst_0 CLKOP_DIV 4
    // exemplar attribute PLLDInst_0 CLKFB_DIV 1
    // exemplar attribute PLLDInst_0 CLKI_DIV 1
    // exemplar attribute PLLDInst_0 FIN 200.000
    // exemplar end

endmodule