ddr_data_io.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: ddr_data_io.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================
`timescale 1ns/100ps
`include "ddr_sdram_mem_params.v"
module ddr_data_io 
  (
   core_clk,
   dqsxfer_clk,
   dqsin_clk,
   rst,
   
   // Input signals from the I/O Bridge
   ddrclkpol,
   ib_write_data,
   ib_ddr_write_en,
   
   // Output signals to the I/O Bridge
   ib_read_data,
   
   // Bi-directional signal at the Memory interface
   bidi
   );
   
//-------------------------------------------------------------------
// Inputs/Outputs 
//-------------------------------------------------------------------
input  	     	                    core_clk;
input  [(`DQS_WIDTH) -1 :0]         dqsxfer_clk;
input  [(`DQS_WIDTH) -1 :0]         dqsin_clk;
input                               rst;
input  [`DQS_WIDTH-1:0]             ddrclkpol;
input  [`DSIZE-1:0]                 ib_write_data;
input  [(`DATA_WIDTH) -1:0]         ib_ddr_write_en;
output [`DSIZE-1:0] 	            ib_read_data;
inout  [`DATA_WIDTH-1:0]            bidi;
   
//-------------------------------------------------------------------
//instantiate bidi_cell
//-------------------------------------------------------------------
   `ifdef DQSD_4
      `define DQSW 4
   `else
      `define DQSW 8
   `endif

   genvar i;   
   generate
     for (i=0; i<`DATA_WIDTH; i=i+1)   
       begin: u
	  bidi_cell bidi_cell
	    (.core_clk(core_clk), 
	     .dqsxfer_clk(dqsxfer_clk[i/`DQSW]), 
	     .dqsin_clk(dqsin_clk[i/`DQSW]), 
	     .rst(rst), 
             .ddrclkpol (ddrclkpol[i/`DQSW]),
	     .d_pos(ib_write_data[i]), 
	     .d_neg(ib_write_data[i+`DATA_WIDTH]), 
	     .out_en(ib_ddr_write_en[i]),
	     .q_pos(ib_read_data[i]), 
	     .q_neg(ib_read_data[i+`DATA_WIDTH]), 
	     .bidi(bidi[i]));
       end // block: u
   endgenerate

endmodule


module bidi_cell (

    core_clk,
    dqsxfer_clk,
    dqsin_clk,
    rst,

    // Input signals to the INDDR module
    ddrclkpol,

    // Input signals to the OUTDDR module
    d_pos,
    d_neg,

    // Input signals to the BB module
    out_en,

    // Output signals from the INDDR module
    q_pos,
    q_neg,

    // Bi-directional signal from the BB module
    bidi
);

//-------------------------------------------------------------------
// Inputs/Outputs 
//-------------------------------------------------------------------
input                 core_clk;
input                 dqsxfer_clk;
input                 dqsin_clk;
input                 rst;
input                 ddrclkpol;
input                 d_pos;
input                 d_neg;
input                 out_en;
output                q_pos;
output                q_neg;
inout                 bidi;
//-------------------------------------------------------------------
// Interconnecting wires
//-------------------------------------------------------------------
wire                  bb_to_in;
wire                  bb_to_in_tmp;
wire                  bb_to_in_tmp1;
wire                  out_to_bb;
wire                  out_en_reg;

//-------------------------------------------------------------------
// I/P Flop 
//-------------------------------------------------------------------
IDDRMFX1A U1_IDDRMFX1A (.D(bb_to_in), .ECLK(dqsin_clk), .CLK1(core_clk), .CLK2(core_clk), .CE(1'b1),
                  .RST(rst), .DDRCLKPOL(ddrclkpol), .QA(q_pos), .QB(q_neg))/* synthesis CLKMODE="SCLK" */;

//-------------------------------------------------------------------
// O/P Flop
//-------------------------------------------------------------------

   ODDRMXA U1_ODDRMXA (.DA(d_pos), .DB(d_neg), .RST(rst), .CLK(core_clk), 
                   .DQSXFER(dqsxfer_clk), .Q(out_to_bb)) /* synthesis CLKMODE="SCLK" */;

//-------------------------------------------------------------------
// O/P Tristate Flop
//-------------------------------------------------------------------

   ODDRMXA U1_TODDRMXA (.DA(out_en), .DB(out_en), .RST(rst), .CLK(core_clk),
                    .DQSXFER(dqsxfer_clk), .Q(out_en_reg)) /* synthesis CLKMODE="SCLK" */;
//-------------------------------------------------------------------
//Parameters for the DQ delay 
//-------------------------------------------------------------------

assign  bb_to_in_tmp1 = bb_to_in_tmp;
assign  bb_to_in = bb_to_in_tmp1;

//-------------------------------------------------------------------
// Instantiate the BB modules
//-------------------------------------------------------------------
BB U1_BB (.I(out_to_bb), .T(out_en_reg), .O(bb_to_in_tmp), .B(bidi));

endmodule