pll_120m.v

DDR2 的控制器

/* Verilog netlist generated by SCUBA ispLever_v70_Prod_Build (55) */
/* Module Version: 3.4 */
/* e:\ispTOOLS7_0\ispfpga\bin\nt\scuba.exe -w -n pll_120M -lang verilog -synth synplify -arch ep5m00 -type pll -fin 80 -phase_cntl STATIC -mdiv 2 -ndiv 3 -vdiv 8 -delay_cntl NO -fb_mode CLOCKTREE -noclkos -kdiv 2 -norst -e  */
/* Tue Oct 09 13:42:50 2007 */


`timescale 1 ns / 1 ps
module pll_120M (CLK, CLKOP, CLKOK, LOCK);
    input CLK;
    output CLKOP;
    output CLKOK;
    output LOCK;

    wire CLK_t;

    VLO scuba_vlo_inst (.Z(scuba_vlo));

    // synopsys translate_off
    defparam PLLDInst_0.CLKOK_BYPASS = "DISABLED" ;
    defparam PLLDInst_0.CLKOK_DIV = 2 ;
    defparam PLLDInst_0.CLKOS_BYPASS = "DISABLED" ;
    defparam PLLDInst_0.CLKOP_BYPASS = "DISABLED" ;
    defparam PLLDInst_0.PHASE_CNTL = "STATIC" ;
    defparam PLLDInst_0.DUTY = 8 ;
    defparam PLLDInst_0.PHASEADJ = "0.0" ;
    defparam PLLDInst_0.CLKOP_DIV = 8 ;
    defparam PLLDInst_0.CLKFB_DIV = 3 ;
    defparam PLLDInst_0.CLKI_DIV = 2 ;
    // synopsys translate_on
    EPLLD PLLDInst_0 (.CLKI(CLK_t), .CLKFB(CLKOP_t), .RST(scuba_vlo), .RSTK(scuba_vlo), 
        .DPAMODE(scuba_vlo), .DRPAI3(scuba_vlo), .DRPAI2(scuba_vlo), .DRPAI1(scuba_vlo), 
        .DRPAI0(scuba_vlo), .DFPAI3(scuba_vlo), .DFPAI2(scuba_vlo), .DFPAI1(scuba_vlo), 
        .DFPAI0(scuba_vlo), .CLKOP(CLKOP_t), .CLKOS(), .CLKOK(CLKOK), .LOCK(LOCK), 
        .CLKINTFB())
             /* synthesis CLKOK_BYPASS="DISABLED" */
             /* synthesis FREQUENCY_PIN_CLKOK="60.000000" */
             /* synthesis CLKOK_DIV="2" */
             /* synthesis CLKOS_BYPASS="DISABLED" */
             /* synthesis FREQUENCY_PIN_CLKOP="120.000000" */
             /* synthesis CLKOP_BYPASS="DISABLED" */
             /* synthesis PHASE_CNTL="STATIC" */
             /* synthesis FDEL="0" */
             /* synthesis DUTY="8" */
             /* synthesis PHASEADJ="0.0" */
             /* synthesis FREQUENCY_PIN_CLKI="80.000000" */
             /* synthesis CLKOP_DIV="8" */
             /* synthesis CLKFB_DIV="3" */
             /* synthesis CLKI_DIV="2" */
             /* synthesis FIN="80.000000" */;

    assign CLKOP = CLKOP_t;
    assign CLK_t = CLK;


    // exemplar begin
    // exemplar attribute PLLDInst_0 CLKOK_BYPASS DISABLED
    // exemplar attribute PLLDInst_0 FREQUENCY_PIN_CLKOK 60.000000
    // exemplar attribute PLLDInst_0 CLKOK_DIV 2
    // exemplar attribute PLLDInst_0 CLKOS_BYPASS DISABLED
    // exemplar attribute PLLDInst_0 FREQUENCY_PIN_CLKOP 120.000000
    // exemplar attribute PLLDInst_0 CLKOP_BYPASS DISABLED
    // exemplar attribute PLLDInst_0 PHASE_CNTL STATIC
    // exemplar attribute PLLDInst_0 FDEL 0
    // exemplar attribute PLLDInst_0 DUTY 8
    // exemplar attribute PLLDInst_0 PHASEADJ 0.0
    // exemplar attribute PLLDInst_0 FREQUENCY_PIN_CLKI 80.000000
    // exemplar attribute PLLDInst_0 CLKOP_DIV 8
    // exemplar attribute PLLDInst_0 CLKFB_DIV 3
    // exemplar attribute PLLDInst_0 CLKI_DIV 2
    // exemplar attribute PLLDInst_0 FIN 80.000000
    // exemplar end

endmodule