ddr_sdram_mem_io_top.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: ddr_sdram_mem_io_top.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================
`timescale 1ns/100ps
`include "ddr_sdram_mem_params.v"
module ddr_sdram_mem_io_top (
   // Inputs
   rst_n,				// System reset

   // Bi-directional databus to external memory
   em_ddr_data,				// DDR data
   em_ddr_dqs,				// DDR data strobes

   // Output to External memory
   // SDRAM Address, controls and clock
   em_ddr_clk,				// DDR clock

   `ifdef DDR2_MODE
       em_ddr_odt,			// DDR2 odt
       ddr_odt_d0,			// Flopped odt
   `else
   `endif
   em_ddr_dm,				// Data mask
   rst_acth,				// Reset active high
   k_clk,				// K clock
   ddr_write_data_valid_d1,		// Flopped write data valid
   ddr_dm_d1,				// Flopped data mask
   dqs_pio_read,			// Data Strobe pio read
   ddr_dqs_out_d0,			// Flopped dqs out
   ddr_dqs_en_d0,			// Flopped dqs enable

   ddr_read_data,
   prmbdet,				// From pio
   dqsi,				// Data stobe from pio
   dqsdel,   		
   ddr_write_data_d1,			// Flopped Write data
   data_valid				// Data valid

);

// ====================================================================
// Define all inputs / outputs
// ====================================================================

input					rst_acth;
input                                  	k_clk;
input					ddr_write_data_valid_d1;
input  	[`USER_DM-1:0]                 	ddr_dm_d1;
input   [`DQS_WIDTH-1:0]                dqs_pio_read;
input  	[(2*`DQS_WIDTH)-1:0]          	ddr_dqs_out_d0;
input					ddr_dqs_en_d0;
input   [`DQS_WIDTH-1:0]	        dqsdel;

input  	[`DSIZE-1:0]                   	ddr_write_data_d1;

`ifdef DDR2_MODE
 `ifdef CS_WIDTH_1
    input                           	ddr_odt_d0;
 `else
    input  [`CS_WIDTH -1 :0]     	ddr_odt_d0;
 `endif
`endif

input                                 	rst_n;
inout  	[`DATA_WIDTH-1:0]              	em_ddr_data;
inout  	[`DQS_WIDTH-1:0]               	em_ddr_dqs;
	
output 	[`DATA_WIDTH/8-1:0]            	em_ddr_dm;
output 	[`CLKO_WIDTH-1:0]              	em_ddr_clk;
output 	[`DSIZE-1:0]                 	ddr_read_data;
`ifdef DATA_SIZE_8
  `ifdef DQSD_4
    output  [(`DQS_WIDTH)-1:0]          data_valid;
  `else    
    output                              data_valid;
  `endif    
`else
    output  [(`DQS_WIDTH)-1:0]          data_valid;
`endif
`ifdef DDR2_MODE
 `ifdef CS_WIDTH_1
    output                        	em_ddr_odt;
 `else
    output  [`CS_WIDTH -1 :0]     	em_ddr_odt;
 `endif
`else
`endif

`ifdef DATA_SIZE_8
`ifdef DQSD_4
   output   [(`DQS_WIDTH)-1:0]         prmbdet;
   output   [(`DQS_WIDTH)-1:0]         dqsi;
`else
    output                              prmbdet;
    output                              dqsi;
`endif    
`else
    output   [(`DQS_WIDTH)-1:0]         prmbdet;
    output   [(`DQS_WIDTH)-1:0]         dqsi;
`endif

// ====================================================================
// Regs & Wires
// ====================================================================
reg                                   	update_cntl;
reg                                   	open_latch;
reg    	[3:0]                          	latch_ctrl_count;

wire 	[`CLKO_WIDTH-1:0]              	em_ddr_clk;
wire                                  	k_clk;
wire    [`DSIZE-1:0]                  	ddr_read_data;

wire   	[`USER_DM-1:0]                 	ddr_dm;
reg    	[`USER_DM-1:0]                 	ddr_dm_d0;
wire   	[`USER_DM-1:0]                 	ddr_dm_d1;
wire   	[`DSIZE-1:0]                   	ddr_write_data;
reg    	[`DSIZE-1:0]                   	ddr_write_data_d0;
wire   	[`DSIZE-1:0]                   	ddr_write_data_d1;
`ifdef DDR2_MODE
 `ifdef CS_WIDTH_1
    wire                           	ddr_odt_d0;
 `else
    wire [`CS_WIDTH -1 :0]     		ddr_odt_d0;
 `endif
`endif
wire                                  	pio_read;
wire                                  	read_command;
`ifdef DATA_SIZE_8
`ifdef DQSD_4
    wire   [(`DQS_WIDTH)-1:0]         	ddrclkpol;
    wire   [(`DQS_WIDTH)-1:0]         	prmbdet;
    wire   [(`DQS_WIDTH)-1:0]         	dqsi;
    wire   [(`DQS_WIDTH)-1:0]         	dqsxfer_clk;
    wire   [(`DQS_WIDTH)-1:0]         	sec_clk;
    wire   [(`DQS_WIDTH)-1:0]         	dqsin_clk;
`else
    wire                              	ddrclkpol;
    wire                              	prmbdet;
    wire                              	dqsi;
    wire                              	dqsxfer_clk;
    wire                              	sec_clk;
    wire                              	dqsin_clk;
`endif    
`else
    wire   [(`DQS_WIDTH)-1:0]         	ddrclkpol;
    wire   [(`DQS_WIDTH)-1:0]         	prmbdet;
    wire   [(`DQS_WIDTH)-1:0]         	dqsi;
    wire   [(`DQS_WIDTH)-1:0]         	dqsxfer_clk;
    wire   [(`DQS_WIDTH)-1:0]         	sec_clk;
    wire   [(`DQS_WIDTH)-1:0]         	dqsin_clk;
`endif

wire  	[(2*`DQS_WIDTH)-1:0]          ddr_dqs_out_d0;
wire                                   ddr_dqs_en_d0;
wire                                   ddr_write_data_valid_d1;
wire  [`DQS_WIDTH-1:0]                  dqsdel;
`ifdef DATA_SIZE_8
   `ifdef DQSD_4
      wire   [(`DQS_WIDTH)-1:0]         data_valid;
   `else
      wire                              data_valid;
   `endif
`else
    wire  [(`DQS_WIDTH)-1:0]          	data_valid;
`endif

// =============================================================================
// Instintiate DDR Data/DQs and DM
// =============================================================================

ddr_data_io U1_ddr_data_io (
  // ------ Inputs -----------
  .core_clk               (k_clk),
  .dqsxfer_clk          (dqsxfer_clk),
  .dqsin_clk              (dqsin_clk),
  .rst                    (rst_acth),
  .ddrclkpol              (ddrclkpol),
  .ib_write_data          (ddr_write_data_d1),
  .ib_ddr_write_en        ({`DATA_WIDTH{ddr_write_data_valid_d1}}),
  
  // ------ Outputs -----------
  .ib_read_data           (ddr_read_data),
  
  // ------ bidir -------------
  .bidi                   (em_ddr_data)
);

ddr_dm_io U1_ddr_dm_io (
  // ------ Inputs -----------
  .core_clk               (k_clk),
`ifdef DATA_SIZE_8
   `ifdef DQSD_4
        .dqsxfer_clk      (dqsxfer_clk[0]),
    `else
        .dqsxfer_clk      (dqsxfer_clk),  
    `endif
`else
        .dqsxfer_clk      (dqsxfer_clk[`DATA_WIDTH/8-1:0]),  
    `endif
  .rst                    (rst_acth),
  .data_in                (ddr_dm_d1),

  // ------ Outputs -----------  
  .ddr_dataout            (em_ddr_dm)
);


ddr_dqs_io U1_ddr_dqs_io (
  // ------ Inputs -----------
  .rst                    (rst_acth),
  .core_clk               (k_clk), // input k_clk
  .pio_read               (dqs_pio_read), // input
  .tri_en                 (ddr_dqs_en_d0), // input 
  .dqsdel                 (dqsdel), // input
  .data_valid             (data_valid),
  .dqsxfer_clk            (dqsxfer_clk), // Output 
  .dqsin_clk              (dqsin_clk),
  .ddr_dqs_out            (ddr_dqs_out_d0), // input
	
  // ------ Oututs -----------	
  .dqsout_core            (), 
  .prmbdet                (prmbdet), 
  .ddrclkpol              (ddrclkpol),  
  .dqsi                   (dqsi), 
	
  // bidir
  .bidi                   (em_ddr_dqs)
);


// ====================================================================
// Generate the clocks for the memory device
// ====================================================================

ODDRXC U1_ODDR_CLK [`CLKO_WIDTH-1:0] (.DA(1'b1), .DB(1'b0), .RST(rst_acth), .CLK(k_clk),
                  .Q(em_ddr_clk))/* synthesis CLKMODE="SCLK" */;


`ifdef DDR2_MODE
ODDRXC U1_ODDR_ODT [`CS_WIDTH-1:0] (.DA(ddr_odt_d0), .DB(ddr_odt_d0), .RST(rst_acth), .CLK(~k_clk),
                  .Q(em_ddr_odt))/* synthesis CLKMODE="SCLK" */;
`endif

endmodule