pio_dvalid_gen.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: pio_dvalid_gen.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================
`timescale 1ns/100ps
`include "ddr_sdram_mem_params.v"

module pio_dvalid_gen 
  (

   // Clock and reset
   clk,
   rst_n,
   // Input signals from the PIO
   prmbdet,      // Preamble detect
   dqsi,         // DQS at the Pad   
   ddrclkpol,    // clock polarity selector
   pio_read,     // Form databusif
   
   // Output signals to the FPGA Logic
   data_valid   // data valid signal
   ) /* synthesis pgroup = "PIO_DVALID_GEN" */;
// exemplar attribute pgroup PIO_DVALID_GEN


//////////////////////////////////////////////////////////////////////////////
// Parameters

//////////////////////////////////////////////////////////////////////////////
//clock and reset inputs
input                                 clk;
input                                 rst_n;

// Input signals from the PIO
input                                 dqsi;
input                                 prmbdet;
input                                 ddrclkpol;

// Input signals from databusif
input                                 pio_read;

// Output signals to the FPGA Logic
output                                data_valid;

// Internal registers and wires
wire                                  data_valid;


data_valid_macro1 u1_data_valid_macro1
  (
   // Inputs
   .prmbdet        (prmbdet),
   .pio_read       (pio_read),
   .dqsi           (dqsi),
    // Output
   .prmbdet_clean  (prmbdet_clean)
   )/* synthesis pgroup="p_data_valid_macro1" */;
// exemplar attribute pgroup p_data_valid_macro1

 data_valid_macro2 u1_data_valid_macro2
  (
   // Inputs
   .rst_n          (rst_n),
   .prmbdet_clean  (prmbdet_clean),
   .dqsi           (dqsi),
   .ddrclkpol      (ddrclkpol),
   .clk            (clk),
   // Output
   .data_valid     (data_valid)
   )/* synthesis pgroup="p_data_valid_macro2" */;
// exemplar attribute pgroup p_data_valid_macro2



endmodule // pio_dvalid_gen



module data_valid_macro1
  (
   prmbdet,
   pio_read,
   dqsi,
 
   prmbdet_clean
   ) /* synthesis syn_hier = "firm" */;
// exemplar attribute data_valid_macro1 hierarchy preserve 

   
input                 prmbdet; //From DQSBUFB block
input                 pio_read; // From core logic
input                 dqsi;//From DQSBUFB block

output                prmbdet_clean;


reg                   prmbdet_raw;
reg                   prmbdet_clean;

wire                  reset_prmbdet_clean;


// =============================================================================
// All the logic in this module should be place in one PFU
// If not routing delays introduced by Isplever may be too high
// and may result in data_valid getting misalligned with data
// =============================================================================
// Detection of preamble rising edge.
// Reset when pio_read is asserted
always @ (posedge prmbdet or posedge pio_read) begin
   if (pio_read) begin
      prmbdet_raw <= 1'b0;
   end
   else begin
      prmbdet_raw <= 1'b1;
   end
end

assign reset_prmbdet_clean = ~ (prmbdet_raw | pio_read);


always @ (negedge dqsi or posedge reset_prmbdet_clean) begin
   if (reset_prmbdet_clean) begin
      prmbdet_clean <= 1'b0;
   end
   else begin
      prmbdet_clean <= prmbdet_raw;
   end
end


endmodule
  
module data_valid_macro2
  (
   rst_n,
   prmbdet_clean,
   dqsi,
   ddrclkpol,
   clk,

   data_valid
   ) /* synthesis syn_hier = "firm" */;
// exemplar attribute data_valid_macro2 hierarchy preserve 

   
input                 rst_n;
input                 prmbdet_clean; //From DQSBUFB block
input                 dqsi;          //From DQSBUFB block
input                 ddrclkpol;     // DDR clk polarity signal from DQSBUFB
input                 clk;

output                data_valid;


reg                   data_valid_pos;
reg                   data_valid_neg;
reg                   data_valid_neg1;
reg                   data_valid;

wire                  reset_data_valid_regs;
wire                  data_valid_comb;


// =============================================================================
// All the logic in this module should be place in one PFU
// If not routing delays introduced by Isplever may be too high
// and may result in data_valid getting misalligned with data
// =============================================================================


assign reset_data_valid_regs = ~prmbdet_clean & dqsi;


always @ (posedge clk or posedge reset_data_valid_regs) begin
   if (reset_data_valid_regs) begin
      data_valid_pos <= 1'b0;
      data_valid_neg1 <= 1'b0;
   end
   else begin
      data_valid_pos <= prmbdet_clean;
      data_valid_neg1 <= data_valid_neg;
   end
end

always @ (negedge clk or posedge reset_data_valid_regs) begin
   if (reset_data_valid_regs) begin
      data_valid_neg <= 1'b0;
   end
   else begin
      data_valid_neg <= prmbdet_clean;
   end
end


assign data_valid_comb = ddrclkpol ? data_valid_neg : data_valid_pos;

always @ (posedge clk or  negedge rst_n) begin
   if (!rst_n) begin
      data_valid <= 1'b0;
   end else begin
      data_valid  <= data_valid_comb;
   end 
end
endmodule