ddr_dm_io.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: ddr_dm_io.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================
`timescale 1ns/100ps
`include "ddr_sdram_mem_params.v"
module ddr_dm_io (
    core_clk,
    dqsxfer_clk,
    rst,
    data_in,
    ddr_dataout
);

//-------------------------------------------------------------------
// Inputs/Outputs 
//-------------------------------------------------------------------
input                          core_clk;
input [(`DATA_WIDTH/8) -1:0]   dqsxfer_clk;
input                          rst;
input [2*(`DATA_WIDTH/8) -1:0] data_in;
output[(`DATA_WIDTH/8) -1:0]   ddr_dataout;

  // Instantiate the ODDRA modules to generate DDR data stream
   genvar i;   
   generate
     for (i=0; i<`DATA_WIDTH/8; i=i+1)   
       begin: u
	    ODDRMXA  ODDRB 
	    (.DB(data_in[i+`DATA_WIDTH/8]), 
	     .DA(data_in[i]), 
	     .CLK(core_clk), 
	     .DQSXFER(dqsxfer_clk[i]), 
	     .RST(rst), 
	     .Q(ddr_dataout[i])) /* synthesis CLKMODE="SCLK" */ ;
	     // exemplar attribute CLKMODE SCLK
     
       end // block: u
   endgenerate

endmodule