📄 cmd_gen.v
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input cmd_valid_lat; //0:de-assert comand valid,
//1:keep cmd_valid asserted
input burst_count;
input row_addr;
input bank_addr;
input col_addr;
integer burst_count;
integer row_addr;
integer bank_addr;
integer col_addr;
begin
@(posedge clk);
cmd = `CDL_READ;
ff_burst_count = burst_count;
addr[`COL_WIDTH-1:0] = col_addr;
addr[`BSIZE+`COL_WIDTH-1:`COL_WIDTH] = bank_addr;
addr[`ROW_WIDTH+`BSIZE+`COL_WIDTH-1:`BSIZE+`COL_WIDTH] = row_addr;
// Stretch the command if the cmd_rdy was sampled asserted.
// This wil prevent the cmd_valid being de-asserted too soon.
@(negedge cmd_rdy);
@(posedge clk);
#1;
cmd_valid = 1'b1;
@(posedge clk);
#1;
@(negedge cmd_rdy);
if (!cmd_valid_lat) begin
@(negedge clk);
cmd_valid = 1'b0;
end
end
endtask
//---------------- Task reada -----------------------------------------
task reada;
input cmd_valid_lat; //0:de-assert comand valid,
//1:keep cmd_valid asserted
input burst_count;
input row_addr;
input bank_addr;
input col_addr;
integer burst_count;
integer row_addr;
integer bank_addr;
integer col_addr;
begin
@(posedge clk);
cmd = `READA;
ff_burst_count = burst_count;
addr[`COL_WIDTH-1:0] = col_addr;
addr[`BSIZE+`COL_WIDTH-1:`COL_WIDTH] = bank_addr;
addr[`ROW_WIDTH+`BSIZE+`COL_WIDTH-1:`BSIZE+`COL_WIDTH] = row_addr;
// Stretch the command if the cmd_rdy was sampled asserted.
// This wil prevent the cmd_valid being de-asserted too soon.
@(negedge cmd_rdy);
@(posedge clk);
#1;
cmd_valid = 1'b1;
@(posedge clk);
#1;
@(negedge cmd_rdy);
if (!cmd_valid_lat) begin
@(negedge clk);
cmd_valid = 1'b0;
end
end
endtask
//---------------- Task write ----------------------------------------
task write;
input cmd_valid_lat; //0:de-assert comand valid,
//1:keep cmd_valid asserted
input burst_count;
input row_addr;
input bank_addr;
input col_addr;
integer burst_count;
integer row_addr;
integer bank_addr;
integer col_addr;
begin
@(posedge clk);
cmd = `CDL_WRITE;
ff_burst_count = burst_count;
addr[`COL_WIDTH-1:0] = col_addr;
addr[`BSIZE+`COL_WIDTH-1:`COL_WIDTH] = bank_addr;
addr[`ROW_WIDTH+`BSIZE+`COL_WIDTH-1:`BSIZE+`COL_WIDTH] = row_addr;
// Stretch the command if the cmd_rdy was sampled asserted.
// This wil prevent the cmd_valid being de-asserted too soon.
@(negedge cmd_rdy);
@(posedge clk);
#1;
cmd_valid = 1'b1;
@(posedge clk);
#1;
@(negedge cmd_rdy);
if (!cmd_valid_lat) begin
@(negedge clk);
cmd_valid = 1'b0;
end
end
endtask
//---------------- Task writea ----------------------------------------
task writea;
input cmd_valid_lat; //0:de-assert comand valid,
//1:keep cmd_valid asserted
input burst_count;
input row_addr;
input bank_addr;
input col_addr;
integer burst_count;
integer row_addr;
integer bank_addr;
integer col_addr;
begin
@(posedge clk);
cmd = `WRITEA;
ff_burst_count = burst_count;
addr[`COL_WIDTH-1:0] = col_addr;
addr[`BSIZE+`COL_WIDTH-1:`COL_WIDTH] = bank_addr;
addr[`ROW_WIDTH+`BSIZE+`COL_WIDTH-1:`BSIZE+`COL_WIDTH] = row_addr;
// Stretch the command if the cmd_rdy was sampled asserted.
// This wil prevent the cmd_valid being de-asserted too soon.
@(negedge cmd_rdy);
@(posedge clk);
#1;
cmd_valid = 1'b1;
@(posedge clk);
#1;
@(negedge cmd_rdy);
if (!cmd_valid_lat) begin
@(negedge clk);
cmd_valid = 1'b0;
end
end
endtask
//---------------- Task check_bl_cl ---------------------------------
task check_bl_cl;
input [2:0] bl_in;
input [2:0] cl_in;
output [2:0] bl_out;
output [2:0] cl_out;
reg [2:0] bl_out;
reg [2:0] cl_out;
begin
if((bl_in !== `BL_2) && (bl_in !== `BL_4) && (bl_in !== `BL_8) &&
(bl_in !== `BL_P)) begin
$display ("cmd_gen ERROR: at time %0t, Illegal Burst Length value %b\n",$time,bl_in);
$display ("cmd_gen ERROR: Allowed values: %b, %b, %b \n", `BL_2, `BL_4, `BL_8, `BL_P);
$display ("cmd_gen ERROR: Burst Length set to 8\n");
bl_out = `BL_8;
end else begin
bl_out = bl_in;
end
`ifdef DDR2_MODE
if((cl_in !== `CL2_0) && (cl_in !== `CL3_0) && (cl_in !== `CL4_0) && (cl_in !== `CL5_0)) begin
$display ("cmd_gen ERROR: at time %0t, Illegal CAS Latency %b\n",$time,cl_in);
$display ("cmd_gen ERROR: Allowed values: %b, %b, %b, %b \n", `CL2_0, `CL3_0, `CL4_0, `CL5_0);
$display ("cmd_gen ERROR: CAS Latency set to 3.0 \n");
cl_out = `CL3_0;
end
else begin
cl_out = cl_in;
end
`else
if((cl_in !== `CL1_5) && (cl_in !== `CL2_0) && (cl_in !== `CL2_5) && (cl_in !== `CL3_0)) begin
$display ("cmd_gen ERROR: at time %0t, Illegal CAS Latency %b\n",$time,cl_in);
$display ("cmd_gen ERROR: Allowed values: %b, %b, %b, %b \n", `CL1_5, `CL2_0, `CL2_5, `CL3_0);
$display ("cmd_gen ERROR: CAS Latency set to 3.0 \n");
cl_out = `CL3_0;
end
else begin
cl_out = cl_in;
end
`endif
end
endtask
//---------------- Task generate_data --------------------------------
task generate_data;
output [`DSIZE+(`DSIZE/8)-1:0] data_out ;
reg [`DSIZE+(`DSIZE/8)-1:0] data_out ;
reg [`DSIZE-1:0] int_data_out ;
reg [7:0] data8 [17:0];
reg [`DSIZE/8-1:0] dm_bits;
reg [`DSIZE/8-1:0] int_dm_bits;
integer i,j;
integer seed;
begin
dm_bits = 16'b0;
for (i=0; i<18; i=i+1) begin
seed = seed+1;
data8[i] = $random(seed);
end
int_dm_bits = {data8[1], data8[0]};
`ifdef DATA_SIZE_32
int_data_out = {data8[7], data8[6], data8[5], data8[4],
data8[3], data8[2], data8[1], data8[0]};
dm_bits[7:0] = int_dm_bits[7:0];
`else
`ifdef DATA_SIZE_16
int_data_out = {data8[3], data8[2], data8[1], data8[0]};
dm_bits[3:0] = int_dm_bits[3:0];
`else
`ifdef DATA_SIZE_8
int_data_out = {data8[1], data8[0]};
dm_bits[1:0] = int_dm_bits[1:0];
`else
`ifdef DATA_SIZE_72
int_data_out = {data8[17], data8[16], data8[15], data8[14], data8[13], data8[12],
data8[11], data8[10], data8[9], data8[8],
data8[7], data8[6], data8[5], data8[4],
data8[3], data8[2], data8[1], data8[0]};
dm_bits = int_dm_bits;
`else
// The default width is 64-bits on memory
int_data_out = {data8[15], data8[14], data8[13], data8[12],
data8[11], data8[10], data8[9], data8[8],
data8[7], data8[6], data8[5], data8[4],
data8[3], data8[2], data8[1], data8[0]};
dm_bits = int_dm_bits;
`endif
`endif
`endif
`endif
data_out = {dm_bits, int_data_out};
end
endtask
//=====================================================================
//------------ Sending data for write/writea tasks --------------------
reg [`DATA_WIDTH*2-1:0] write_data;
reg datain_valid_d;
reg [((`DATA_WIDTH*2)/8)-1:0] data_mask;
always@ (posedge clk) begin
if(rst_n == 0) begin
datain_valid_d <= 1'b0;
end
else begin
datain_valid_d <= datain_valid;
if(datain_valid) begin
generate_data({data_mask,write_data});
end
else if (datain_valid_d) begin
write_data = 0;
data_mask = 0;
end
end
end
always @ (write_data) begin
datain = #1 write_data;
end
always @ (data_mask or dm_toggle) begin
if (dm_toggle)
dmsel = #1 data_mask;
else
dmsel = 16'b0;
end
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