cmd_gen.v

DDR2 的控制器

// $Id: testbench/cmd_gen.v 1.1 2006/05/05 10:00:17PDT skotini Exp  $
// =============================================================================
//                           COPYRIGHT NOTICE
// Copyright 2000-2001 (c) Lattice Semiconductor Corporation
// ALL RIGHTS RESERVED
// This confidential and proprietary software may be used only as authorised by
// a licensing agreement from Lattice Semiconductor Corporation.
// The entire notice above must be reproduced on all authorized copies and
// copies may only be made to the extent permitted by a licensing agreement from
// Lattice Semiconductor Corporation.
//
// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
// 5555 NE Moore Court                            408-826-6000 (other locations)
// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
// U.S.A                                   email: [e-mail]
// =============================================================================
//                        FILE DETAILS
// Project          : DDR_MACO SDRAM Controller
// File             : cmd_gen.v
// Title            : Command generator tasks
// Dependencies     : ddr_sdram_mem_params.v
// Description      : This module includes all the tasks used to generate
//                    commands on the User interface.
// =============================================================================

///////////////////////////////////////////////////////////////////////
// Supported commands
// read          (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)
// write         (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)
// reada         (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)
// writea        (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)
// self_ref      (cmd_valid_lat)
// load_mr       (cmd_valid_lat, bl, bt, cl, op)
// load_emr      (cmd_valid_lat, dll_disable, drive_strength)
// pdown         (cmd_valid_lat)
// init          ()
// burst_term    ()
//////////////////////////////////////////////////////////////////////

//---------------- Task reset ------------------------------------
task reset;
begin
  // Assert reset
  rst_n             = 0;

  // De-assert reset after 200 clock cycles
  #(200*c) rst_n    = 1;
end
endtask

//---------------- Task init ------------------------------------
// This task provides a initialization request
task init;
begin
  // Assert init_start
   @(posedge clk);
   init_start   = 1;
   while (!init_done) @ (posedge clk);
   init_start   = 0;
end
endtask

//---------------- Task burst_term ------------------------------------
// This task asserts teh burst terminate signal
task burst_term;
begin
   @(posedge clk);
   ff_burst_term   = 1;
   @ (posedge clk);
   ff_burst_term   = 0;
end
endtask

//---------------- Task pdown -------------------------------------
// This task issues the powerdown command.
task pdown; 
input        cmd_valid_lat;   //0:de-assert comand valid, 
			      //1:keep cmd_valid asserted
begin
   @(posedge clk);
   cmd     = `PWRDN;
   // Stretch the command if the cmd_rdy was sampled asserted.
   // This wil prevent the cmd_valid being de-asserted too soon.
   @(negedge cmd_rdy);
   @(posedge clk);
   #1;
   cmd_valid   = 1'b1;
   @(posedge clk);
   #1;
   @(negedge cmd_rdy);

   if (!cmd_valid_lat) begin
       @(negedge clk);
       cmd_valid = 1'b0;
   end
end
endtask
//---------------- Task load_emr -------------------------------------
`ifdef DDR2_MODE

task load_emr ;
input        cmd_valid_lat;   //0:de-assert comand valid,
			      //1:keep cmd_valid asserted
input        dll_disable;     //0:enable, 1:disable
input        drive_strength;   
input [1:0]  rtt;   
input [2:0]  add_lat;   
input [2:0]  ocd;   
input        diff_dqs_dis;   
input        rdqs_en;   
input        out_disable;   

begin
   @(posedge clk);
   cmd         = `LOAD_MR;
   addr[0]     = dll_disable;
   addr[1]     = drive_strength;
   addr[2]     = rtt[0];
   addr[5:3]   = add_lat;
   addr[6]     = rtt[1];
   addr[9:7]   = ocd;
   addr[10]    = diff_dqs_dis;
   addr[11]    = rdqs_en;
   addr[12]    = out_disable;
   addr[14:13] = 2'b01;   //00:MR  01:EMR
   // Stretch the command if the cmd_rdy was sampled asserted.
   // This wil prevent the cmd_valid being de-asserted too soon.
   @(negedge cmd_rdy);
   @(posedge clk);
   #1;
   cmd_valid   = 1'b1;
   @(posedge clk);
   #1;
   @(negedge cmd_rdy);

   if (!cmd_valid_lat) begin
       @(negedge clk);
       cmd_valid = 1'b0;
   end
end
endtask

`else

task load_emr ;
input        cmd_valid_lat;   //0:de-assert comand valid,
			      //1:keep cmd_valid asserted
input        dll_disable;     //0:enable, 1:disable
input        drive_strength;   
begin
   @(posedge clk);
   cmd         = `LOAD_MR;
   addr[0]     = dll_disable;
   addr[1]     = drive_strength;
   addr[10:2]  = 9'b0;
   addr[12:11] = 2'b10;   //00:MR  10:EMR
   // Stretch the command if the cmd_rdy was sampled asserted.
   // This wil prevent the cmd_valid being de-asserted too soon.
   @(negedge cmd_rdy);
   @(posedge clk);
   #1;
   cmd_valid   = 1'b1;
   @(posedge clk);
   #1;
   @(negedge cmd_rdy);

   if (!cmd_valid_lat) begin
       @(negedge clk);
       cmd_valid = 1'b0;
   end
end
endtask

`endif
//---------------- Task load_mr --------------------------------------
`ifdef DDR2_MODE

task load_mr;
input        cmd_valid_lat;   //0:de-assert comand valid,
                              //1:keep cmd_valid asserted
input[2:0]   bl;
input        bt;
input[2:0]   cl;
input        op;
input[2:0]   wr_rec;
input        pd_mode;

reg  [2:0]   bl_bits;
reg  [2:0]   cl_bits;
begin
   @(posedge clk);
   cmd         = `LOAD_MR;
   check_bl_cl (bl, cl, bl_bits, cl_bits);
   addr[2:0]   = bl_bits;
   addr[3]     = bt;
   addr[6:4]   = cl_bits;
   addr[7]     = LOW;
   addr[8]     = op;
   addr[11:9]  = wr_rec;
   addr[12]    = pd_mode;
   addr[14:13] = 2'b00;
   // Stretch the command if the cmd_rdy was sampled asserted.
   // This wil prevent the cmd_valid being de-asserted too soon.
   @(negedge cmd_rdy);
   @(posedge clk);
   #1;
   cmd_valid   = 1'b1;
   @(posedge clk);
   #1;
   @(negedge cmd_rdy);

   if (!cmd_valid_lat) begin
       @(negedge clk);
       cmd_valid = 1'b0;
   end
end
endtask

`else

task load_mr;
input        cmd_valid_lat;   //0:de-assert comand valid,
                              //1:keep cmd_valid asserted
input[2:0]   bl;
input        bt;
input[2:0]   cl;
input        op;

reg  [2:0]   bl_bits;
reg  [2:0]   cl_bits;
begin
   @(posedge clk);
   cmd         = `LOAD_MR;
   check_bl_cl (bl, cl, bl_bits, cl_bits);
   addr[2:0]   = bl_bits;
   addr[3]     = bt;
   addr[6:4]   = cl_bits;
   addr[8]     = op;
   addr[10:9]  = 2'b00;
   addr[12:11] = 2'b00;   //00:MR  10:EMR
   // Stretch the command if the cmd_rdy was sampled asserted.
   // This wil prevent the cmd_valid being de-asserted too soon.
   @(negedge cmd_rdy);
   @(posedge clk);
   #1;
   cmd_valid   = 1'b1;
   @(posedge clk);
   #1;
   @(negedge cmd_rdy);

   if (!cmd_valid_lat) begin
       @(negedge clk);
       cmd_valid = 1'b0;
   end
end
endtask

`endif
//---------------- Task self_ref --------------------------------------
task self_ref;
input        cmd_valid_lat;   //0:de-assert comand valid,
                              //1:keep cmd_valid asserted

begin
   @(posedge clk);
   cmd         = `SEFL_REF;
   // Stretch the command if the cmd_rdy was sampled asserted.
   // This wil prevent the cmd_valid being de-asserted too soon.
   @(negedge cmd_rdy);
   @(posedge clk);
   #1;
   cmd_valid   = 1'b1;
   @(posedge clk);
   #1;
   @(negedge cmd_rdy);
   
   if (!cmd_valid_lat) begin
       @(negedge clk);
       cmd_valid = 1'b0;
       end
end
endtask
//---------------- Task read  -----------------------------------------
// read          (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)
// This task issues the read command.
task read ;