testcase.v

DDR2 的控制器

// ===========================================================================
// Verilog module generated by IPexpress
// Filename: testcase.v  
// Copyright 2006 (c) Lattice Semiconductor Corporation. All rights reserved.
// ===========================================================================

// load_mr       (cmd_valid_lat, bl, bt, cl, op)
// write         (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)
// read          (cmd_valid_lat, burst_count, row_addr, bank_addr, col_addr)

`ifdef BRST_CNT_EN
   parameter MAX_BURST_CNT = 32;
`else
   parameter MAX_BURST_CNT = 1;
`endif
parameter MAX_CMD_CNT = 8;
parameter TB_COL_CNT = 1 << `COL_WIDTH;   
parameter MAX_BA_CNT = 1 << `BSIZE;



integer                bt_cnt;
reg [3:0]              curr_bl_cnt;
reg [2:0]              bl_cnt;
reg [`BSIZE :0]        ba_cnt;
reg [`BSIZE :0]        curr_ba_cnt;
reg [`BSIZE -1 :0]     ba_addr;
reg [`COL_WIDTH-1:0]   col_addr;


reg [31:0]             wr_cmd_cnt;
reg [31:0]             wr_addr;
reg [31:0]             wr_start_addr;

reg [`ROW_WIDTH+`BSIZE+`COL_WIDTH-1:`BSIZE+`COL_WIDTH] row_addr;

`ifdef DDR2_MODE
   parameter BL_CNT_STRT = 2;
`else
   parameter BL_CNT_STRT = 1;
`endif


initial begin
    reset;
    #(20*c);
    init;
    #(20*c);
    @(posedge clk);
    #1;

    `ifdef DDR2_MODE
       //load_mr       (cmd_valid, bl[2:0], bt, `TB_DDR_CL, op, wr_rec, pd_mode);
       load_mr       (0, 2, LOW, `TB_DDR_CL, LOW, `TB_DDR2_WR_RECOV, LOW);
    `else
       load_mr       (0, 2, 0, `TB_DDR_CL, 0);
    `endif

    //////////////////////////////////////////////////////////
    // All Commands Individually 
    //////////////////////////////////////////////////////////


    pdown         (0);
    #(250*c);

    self_ref      (0);
    #(250*c);

    write       (0, 1, 3, 2, 8);
    #(250*c);

    writea       (0, 1, 4, 2, 8);
    #(250*c);
    writea       (0, 1, 4, 3, 8);
    #(250*c);
    writea       (0, 1, 4, 0, 8);
    #(250*c);
    writea       (0, 1, 4, 1, 8);
    #(250*c);
    writea       (0, 1, 5, 2, 8);
    #(250*c);

    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 4, 2, 8);
    reada       (0, 1, 4, 3, 8);
    reada       (0, 1, 4, 0, 8);
    reada       (0, 1, 4, 1, 8);
    `endif

    #(250*c);
    read       (0, 1, 4, 2, 8);
    read       (0, 1, 4, 3, 8);
    read       (0, 1, 5, 2, 8);

    #(250*c);

    // RD - RD
    read       (0, 1, 3, 2, 8);
    read       (0, 1, 3, 2, 8);
    #(250*c);

    // RD - RDA
    read       (0, 1, 3, 2, 8);
    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 2, 8);
    `endif
    #(250*c);

    // RD - RD
    read       (0, 1, 3, 2, 8);
    read       (0, 1, 3, 2, 8);
    #(250*c);

    // RDA - RD
    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 2, 8);
    `endif
    read       (0, 1, 3, 2, 8);
    #(250*c);

    // RDA - RDA
    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 2, 8);
    reada       (0, 1, 3, 2, 8);
    `endif
    #(250*c);


    // RD - WR
    read       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 2, 8);
    #(250*c);


    // RDA - WR
    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 2, 8);
    `endif
    write       (0, 1, 3, 2, 8);
    #(250*c);

    // RD - ACT  -- Different Bank
    read       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 1, 8);
    #(250*c);

    // RDA - ACT  -- Different Bank
    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 2, 8);
    `endif
    write       (0, 1, 3, 3, 8);
    #(250*c);

    // RDA - ACT  -- Same Bank 
    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 2, 8);
    `endif
    write       (0, 1, 3, 2, 8);
    #(250*c);

    // RD - ACT  -- Same Bank - Not Possible

    // RD - PRE - ACT 
    read       (0, 1, 3, 2, 8);
    write       (0, 1, 2, 2, 8);
    #(250*c);


    `ifdef DDR2_MODE
       //load_mr       (cmd_valid, bl[2:0], bt, `TB_DDR_CL, op, wr_rec, pd_mode);
       load_mr       (0, 2, LOW, `TB_DDR_CL, LOW, `TB_DDR2_WR_RECOV, LOW);
    `else
       load_mr       (0, 2, 0, `TB_DDR_CL, 0);
    `endif

    // WR - WR
    write       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 2, 8);
    #(20*c);
    read       (0, 1, 3, 2, 8);
    read       (0, 1, 3, 2, 8);
    #(250*c);



    // WR - WRA
    write       (0, 1, 3, 2, 8);
    writea       (0, 1, 3, 2, 8);
    #(250*c);


    // WR - WR
    write       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 2, 8);
    #(250*c);


    // WRA - WR -- Same bank
    writea       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 2, 8);
    #(250*c);

    // WRA - WR -- Diff bank without ACT 
    write       (0, 1, 3, 3, 8);
    writea       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 3, 8);
    #(250*c);

    // WRA - WRA  -- Same Bank
    writea       (0, 1, 3, 2, 8);
    writea       (0, 1, 3, 2, 8);
    #(250*c);

    // WRA - WRA  -- Diff Bank
    writea       (0, 1, 3, 2, 8);
    writea       (0, 1, 3, 3, 8);
    #(250*c);

    // WR - RD -- Same Bank
    write       (0, 1, 3, 2, 8);
    read        (0, 1, 3, 2, 8);
    #(250*c);

    // WR - RD -- Diff Bank
    write       (0, 1, 3, 3, 8);
    read        (0, 1, 3, 2, 8);
    #(250*c);

    // WRA - RD  -- Diff Bank
    writea       (0, 1, 3, 3, 8);
    read        (0, 1, 3, 2, 8);
    #(250*c);


    // WRA - RD  -- Same Bank
    writea       (0, 1, 3, 3, 8);
    read        (0, 1, 3, 3, 8);
    #(250*c);


    // WRA - WRA - ACT - RD  -- Diff Bank
    writea       (0, 1, 3, 2, 8);
    writea       (0, 1, 3, 3, 8);
    read        (0, 1, 3, 2, 8);
    #(250*c);


    // WR - RDA  -- Same Bank
    write       (0, 1, 3, 2, 8);
    `ifdef ECP_20_ONLY
    `else
    reada        (0, 1, 3, 2, 8);
    `endif
    #(250*c);


    // WR - RDA  -- Diff Bank
    write       (0, 1, 3, 2, 8);
    #(20*c);
    write       (0, 1, 3, 3, 8);
    `ifdef ECP_20_ONLY
    `else
    reada        (0, 1, 3, 2, 8);
    `endif
    #(250*c);


    // WRA - RDA  -- Same Bank
    writea       (0, 1, 3, 2, 8);
    `ifdef ECP_20_ONLY
    `else
    reada        (0, 1, 3, 2, 8);
    `endif
    #(250*c);

    // WRA - RDA  -- Diff Bank
    write       (0, 1, 3, 2, 8);
    #(20*c);
    writea       (0, 1, 3, 3, 8);
    `ifdef ECP_20_ONLY
    `else
    reada        (0, 1, 3, 2, 8);
    `endif
    #(250*c);




    // WR - ACT  -- Different Bank
    write       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 1, 8);
    write       (0, 1, 3, 0, 8);
    write       (0, 1, 3, 3, 8);
    #(250*c);


    // WRA - ACT  -- Different Bank
    writea       (0, 1, 3, 3, 8);
    #(20*c);
    writea       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 3, 8);
    #(250*c);


    // WRA - ACT  -- Same Bank 
    writea       (0, 1, 3, 2, 8);
    write       (0, 1, 3, 2, 8);
    #(250*c);


    // WR - ACT  -- Same Bank - Not Possible

    // WR - PRE - ACT 
    write       (0, 1, 3, 2, 8);
    write       (0, 1, 2, 2, 8);
    #(250*c);


    writea       (0, 1, 3, 3, 16);
    #(250*c);


    `ifdef ECP_20_ONLY
    `else
    reada       (0, 1, 3, 3, 16);
    `endif
    #(250*c);
   

    $display ("%m : %t INFO: All Commands Section is DONE", $time);
    ////////////ALL Commands DONE ///////////////////////////////

    ////////////////////////////////////////////////////////////////////////
    // Try Different Burst Count here 
    // For all the Burst Lengths
    ////////////////////////////////////////////////////////////////////////


    for (bl_cnt = BL_CNT_STRT; bl_cnt < 4; bl_cnt = bl_cnt + 1) begin 
       // Precharge all the banks
       // And load new BL
    `ifdef DDR2_MODE
       //load_mr       (bl[2:0], bt, `TB_DDR_CL, op, wr_rec, pd_mode);
       load_mr       (0, bl_cnt, LOW, `TB_DDR_CL, LOW, `TB_DDR2_WR_RECOV, LOW);
    `else
       load_mr       (0, bl_cnt, 0, `TB_DDR_CL, 0);
    `endif

       #(250*c);
       curr_bl_cnt = bl_cnt == 3 ? 8 : bl_cnt *2;

       // Enable Data Mask Signal toggling
       dm_toggle = 1;
       $display ("%t INFO : data mask is enabled", $time); 
       for (bt_cnt = 1; bt_cnt < 30; bt_cnt = bt_cnt + 1) begin
          ba_addr = bt_cnt [1:0];
          col_addr = bt_cnt*curr_bl_cnt ;
          $display ("%0t INFO : bt_cnt is %0d", $time, bt_cnt); 
          #(250*c);
          write       (0, 1, 2, ba_addr, col_addr);
       end

       #(250*c);



       // Disable Data Mask Signal toggling
       dm_toggle = 0;
       $display ("%t INFO : data mask is disabled", $time); 
       for (bt_cnt = 1; bt_cnt < MAX_BURST_CNT; bt_cnt = bt_cnt + 1) begin
          ba_addr = bt_cnt [1:0];
          col_addr = bt_cnt*curr_bl_cnt ;
          $display ("%0t INFO : bt_cnt is %0d", $time, bt_cnt); 

          #(250*c);
          write       (0, bt_cnt, 2, ba_addr, col_addr);
          read       (0, bt_cnt, 2, ba_addr, col_addr);
       end

    end

    #(100*c);
    $display ("%m : %t INFO: Burst Cnt Section is DONE", $time);

   # (1000*c);


    //////////// Burst Count DONE ///////////////////////////////
    
    ////////////////////////////////////////////////////////////////////////
    // Check Bank Management and Timing Parameters here 
    ////////////////////////////////////////////////////////////////////////
    // Generate continuous address so as to change BA and to get ACT 
    // Check the WR --> ACT --> WR Sequence
    // Generate continuous address so as to change BA and ROW and to get PRE, ACT 
    // Check the PRE --> ACT --> --> WR Sequence

    for (bl_cnt = BL_CNT_STRT; bl_cnt < 4; bl_cnt = bl_cnt + 1) begin 
       // Precharge all the banks
       // And load new BL
    `ifdef DDR2_MODE
       //load_mr       (bl[2:0], bt, `TB_DDR_CL, op, wr_rec, pd_mode);
       load_mr       (0, bl_cnt, LOW, `TB_DDR_CL, LOW, `TB_DDR2_WR_RECOV, LOW);
    `else
       load_mr       (0, bl_cnt, 0, `TB_DDR_CL, 0);
    `endif

       #(250*c);
       curr_bl_cnt = (bl_cnt == 3) ? 8 : bl_cnt *2;
       $display ("%m : %t INFO: Selecting BL = %0d", $time, curr_bl_cnt);

       for (ba_cnt = 0; ba_cnt < MAX_BA_CNT; ba_cnt = ba_cnt + 1) begin 
          curr_ba_cnt = ba_cnt;
          $display ("%m : %t INFO: Selecting BANK = %0d", $time, curr_ba_cnt);

          // Transition From BA0 to BA1 
          wr_start_addr = 'd504 + curr_ba_cnt*TB_COL_CNT;
          for (wr_cmd_cnt = 0; wr_cmd_cnt <= MAX_CMD_CNT; wr_cmd_cnt = wr_cmd_cnt + 1) begin
             wr_addr = wr_cmd_cnt*curr_bl_cnt + wr_start_addr;
             {row_addr, ba_addr, col_addr [`TB_DDR_COL -1 :0]} = wr_addr;       // This is good the for the Micro model
             write       (0, 1, row_addr, ba_addr, col_addr);
          end
          #(25*c);
       end

       #(250*c);
       $display ("%m : %t INFO: Entering Selecting BANK = %0d", $time, curr_ba_cnt);

       for (ba_cnt = 0; ba_cnt < MAX_BA_CNT; ba_cnt = ba_cnt + 1) begin 
          curr_ba_cnt = ba_cnt;
          $display ("%m : %t INFO: Selecting BANK = %0d", $time, curr_ba_cnt);

          // Transition From BA0 to BA1 
          wr_start_addr = 'd504 + (MAX_BA_CNT + curr_ba_cnt)*TB_COL_CNT;
          for (wr_cmd_cnt = 0; wr_cmd_cnt <= MAX_CMD_CNT; wr_cmd_cnt = wr_cmd_cnt + 1) begin
             wr_addr = wr_cmd_cnt*curr_bl_cnt + wr_start_addr;
             {row_addr, ba_addr, col_addr [`TB_DDR_COL -1:0]} = wr_addr;       // This is good the for the Micro model
             write       (0, 1, row_addr, ba_addr, col_addr);
          end
          #(25*c);
       end


    end

    $display ("%m : %t INFO: Bank Management Section is DONE", $time);

    /////////////////////////////////////////////////////////
    /////////////////////////////////////////////////////////
    #(200*c);
    endoftest = 1;
    #c;
    endoftest = 0;
    $stop;
end