tb_config_params.v

来自「DDR2 的控制器」· Verilog 代码 · 共 181 行

// ====================================================================
// Same as 8 bit case
// ====================================================================
`ifdef DATA_SIZE_72
   `ifdef DDR2_MODE
   
      `ifdef SLAYER
        `define sg37E
      `else
        `define sg5E
      `endif
      `define x8
      `define TB_DDR_CL 3'b100
      `define TB_DSIZE 72*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      `define TB_DDR2_WR_RECOV 3 	 	// to get value of 4 we need to set it to 3  
      
   `else
   
      `define sg5B
      `define x8
      `define TB_DDR_CL 3'b010
      `define TB_DSIZE 72*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      
   `endif
`endif

`ifdef DATA_SIZE_64
   `ifdef DDR2_MODE
   
      `ifdef SLAYER
        `define sg37E
      `else
        `define sg5E
      `endif
      `define x8
      `define TB_DDR_CL 3'b100
      `define TB_DSIZE 64*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      `define TB_DDR2_WR_RECOV 3 	 	// to get value of 4 we need to set it to 3  
      
   `else
   
      `define sg5B
      `define x8
      `define TB_DDR_CL 3'b010
      `define TB_DSIZE 64*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      
   `endif
`endif

`ifdef DATA_SIZE_32
   `ifdef DDR2_MODE
   
      `ifdef SLAYER
        `define sg37E
      `else
        `define sg5E
      `endif
      `define x8
      `define TB_DDR_CL 3'b100
      `define TB_DSIZE 32*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      `define TB_DDR2_WR_RECOV 3 	 	// to get value of 4 we need to set it to 3  
      
   `else
   
      `define sg5B
      `define x8
      `define TB_DDR_CL 3'b010
      `define TB_DSIZE 32*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      
   `endif
`endif

`ifdef DATA_SIZE_16
   `ifdef DDR2_MODE
   
      `ifdef SLAYER
        `define sg37E
      `else
        `define sg5E
      `endif
      `define x8
      `define TB_DDR_CL 3'b100
      `define TB_DSIZE 16*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      `define TB_DDR2_WR_RECOV 3 	 	// to get value of 4 we need to set it to 3  
      
   `else
   
      `define sg5B
      `define x8
      `define TB_DDR_CL 3'b010
      `define TB_DSIZE 16*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      
    `endif
`endif


`ifdef DATA_SIZE_8
   `ifdef DDR2_MODE
   
       `ifdef SLAYER
        `define sg37E
      `else
        `define sg5E
      `endif
      `define x8
      `define TB_DDR_CL 3'b100
      `define TB_DSIZE 8*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      `define TB_DDR2_WR_RECOV 3 	 	// to get value of 4 we need to set it to 3  
      
   `else
   
      `define sg5B
      `define x8
      `define TB_DDR_CL 3'b010
      `define TB_DSIZE 8*2
      `define TB_DDR_ROW `ROW_WIDTH
      `define TB_DDR_COL `COL_WIDTH
      
   `endif
`endif

// ====================================================================
// This is used only in the reduced memory mode
// ====================================================================

`define BL_2       3'b001
`define BL_4       3'b010
`define BL_8       3'b011
`define BL_P       3'b111

`define CL1_5      3'b101
`define CL2_0      3'b010
`define CL2_5      3'b110
`define CL3_0      3'b011
`define CL4_0      3'b100
`define CL5_0      3'b101

// ====================================================================
// Delay the ras, cas, cs and we signals to prevent hold timing violations 
// in the functional simulation
// These numbers should be deleted for timing simulations.
// ====================================================================

`ifdef DATA_SIZE_72
    `define HOLD_DLY 1 
`endif

`ifdef DATA_SIZE_64
    `define HOLD_DLY 1 
`endif

`ifdef DATA_SIZE_32
    `define HOLD_DLY 1
`endif

`ifdef DATA_SIZE_16
    `define HOLD_DLY 1 
`endif

`ifdef DATA_SIZE_8
    `define HOLD_DLY 1
`endif