monitor.v

DDR2 的控制器

   always @ (posedge clk_1 or negedge rst_n) begin
`else
`ifdef ECP2
   wire clk_1;
   assign #1 clk_1 = clk;
   always @ (posedge clk_1 or negedge rst_n) begin
`else
always @ (posedge clk or negedge rst_n) begin
`endif
`endif
    if (!rst_n) begin
	usr_read_cnt          <= 0;
	usr_write_cnt         <= 0;
	wr_cmd_clkcnt         <= 0;
	rd_cmd_clkcnt         <= 0;
    end
    else begin
	// count the number of read/write commands issued at the 
	// user interface

	if (cmd_rdy && cmd_valid && 
	    ((cmd == 4'b0010) || (cmd == 4'b0100)))
            usr_write_cnt     <= usr_write_cnt + burst_cnt;

	if (cmd_rdy && cmd_valid && 
	    ((cmd == 4'b0001) || (cmd == 4'b0011)))
               usr_read_cnt      <= usr_read_cnt + burst_cnt;

	// count the number of read/write commands seen on the 
	// memory interface

	//if (mem_wr_cmd)
	//    mem_write_cnt     <= mem_write_cnt + 1;
	//if (mem_rd_cmd)
	//    mem_read_cnt      <= mem_read_cnt + 1;

        // Count the number of clock cycles where the user supplied
	// commands are more than those seen on the mem interface

	if (usr_write_cnt > mem_write_cnt) begin
	    if (mem_wr_cmd)
	        wr_cmd_clkcnt     <= 0;
	    else
	        wr_cmd_clkcnt     <= wr_cmd_clkcnt + 1;
	end
	else if (mem_write_cnt == usr_write_cnt)
	    wr_cmd_clkcnt     <= 0;

	if (usr_read_cnt > mem_read_cnt)
	    if (mem_rd_cmd)
		rd_cmd_clkcnt     <= 0;
	    else 
	        rd_cmd_clkcnt     <= rd_cmd_clkcnt + 1;
	else if (mem_read_cnt == usr_read_cnt)
	    rd_cmd_clkcnt     <= 0;
    end
end

always @ (wr_cmd_clkcnt) begin
    if (wr_cmd_clkcnt > 2000) begin
        $display ("MON ERROR: At time %0t, more than 2000 clocks elapsed without a write cycle.  Ending test.\n", $time);
        mon_endoftest     = 1;
	$finish;
    end
end

always @ (rd_cmd_clkcnt) begin
    if (rd_cmd_clkcnt > 2000) begin
        $display ("MON ERROR: At time %0t, more than 2000 clocks elapsed without a read cycle.  Ending test.\n", $time);
        mon_endoftest     = 1;
	$finish;
    end
end

always @ (endoftest or mon_endoftest) begin
    if (endoftest || mon_endoftest) begin
        if (usr_read_cnt != mem_read_cnt) begin
            $display ("MON ERROR: At the end of test, Read commands on user interface is %0d, memory interface is %0d\n", usr_read_cnt, mem_read_cnt);
        end
        if (usr_write_cnt != mem_write_cnt) begin
            $display ("MON ERROR: At the end of test, Write commands on user interface is %0d, memory interface is %0d\n", usr_write_cnt, mem_write_cnt);
        end
    end
end

always @ (posedge clk or negedge rst_n) begin
    if (!rst_n) begin
	mem_read_cnt          <= 0;
	mem_write_cnt         <= 0;
    end
    else begin
	// count the number of read/write commands seen at the memory
	// interface
        `ifdef ECP_20_ONLY
         // Don't count if new cmd comes and non_cs_rd is asserted
         // Count +1 if only new cmd comes
         // count -1 if only non_cs_rd is asserted   
	   if (mem_rd_cmd && non_cs_rd)
	       mem_read_cnt      <= mem_read_cnt;
	   else if (mem_rd_cmd)
	       mem_read_cnt      <= mem_read_cnt + 1;
	   else if (non_cs_rd)
	       mem_read_cnt      <= mem_read_cnt - 1;
        `else
	   if (mem_rd_cmd)
	       mem_read_cnt      <= mem_read_cnt + 1;
        `endif  
	
	if (mem_wr_cmd)
	    mem_write_cnt     <= mem_write_cnt + 1;
    end
end

///////////////////////////////////////////////////////////////////////
// Logic that monitors the initialization sequence

///////////////////////////////////////////////////////////////////////
// Logic to ensure auto refresh commands are issued periodically at 
// proper intervals.

// Once the initialization process ends, the refresh period starts.  
// This logic flags an error if an auto refresh cycle was not asserted
// before the period was over.  While the self ref period is in place, 
// the refresh counter stops and resumes once the memory device is ready 
// to accept commands again

integer           ref_period_cnt;   // counts the clocks between refresh commands
reg               mem_sref_cmd_sth;
wire       [3:0]  int_ar_burst_en;
integer           aref_cmd_cnt;   // counts the number of aref commands 

assign int_ar_burst_en = (|ar_burst_en) ? {1'b0,ar_burst_en} 
					: 4'b1000;

always @ (posedge clk) begin
    if (!rst_n) begin
	mem_sref_cmd_sth      <= 0;
    end
    else begin
        if (mem_aref_cmd || mem_sref_cmd) begin
	    ref_period_cnt    <= 0;
        end
        else begin
	    mem_sref_cmd_sth  <= (mem_sref_cmd | mem_sref_cmd_sth) &
				 (~(mem_rd_cmd | mem_wr_cmd | mem_pd_cmd |
				    mem_lmr_cmd | mem_act_cmd | mem_pre_cmd));

	    // Do not increment counter while in self refresh state
	    if (!mem_sref_cmd_sth)
	        ref_period_cnt    <= ref_period_cnt + 1;
        end

        if (ref_period_cnt >= (int_ar_burst_en*trefi)) begin
	    $display("MON ERROR: At time %0t, Auto refresh not asserted for %0d clock cycles\n", $time, (int_ar_burst_en*trefi));
	    ref_period_cnt    <= 0;
        end

        // This logic counts the number of auto refresh cycles

        if (mem_aref_cmd)
	    aref_cmd_cnt      <= aref_cmd_cnt + 1;

        else if (mem_sref_cmd | mem_rd_cmd | mem_wr_cmd | mem_pd_cmd |
	         mem_lmr_cmd | mem_act_cmd | mem_pre_cmd) begin
	    aref_cmd_cnt      <= 0;
	    
	    if (aref_cmd_cnt != 0)
		// Perform check only outside init sequence.
		if (~init_start && (aref_cmd_cnt != int_ar_burst_en))
		    $display ("MON ERROR: At time %0t, Auto Refresh command gen error.  Expected number is %0d, actual is %0d\n",$time,int_ar_burst_en, aref_cmd_cnt);
        end

    end
end

///////////////////////////////////////////////////////////////////////
// Logic that compares the data presented at the user interface with the 
// data written into the memory during write cycles

reg   [143+18:0]         wr_data_fifo    [0:15];
reg   [3:0]              wdf_wr_addr;
reg   [3:0]              wdf_rd_addr;
reg                      mem_wr_cmd_lat;
reg   [143+18:0]         wr_data_fifo_out;
reg   [71:0]             data_posedge;
reg   [8:0]              mask_posedge;
reg                      datain_valid_d;

wire  [143+18:0]         int_wr_data_compare;
wire  [17:0]             wr_dm_compare;
wire  [17:0]             int_wr_dm_compare;
wire  [143:0]            wr_data_compare;
// Write the data submitted by the user into the fifo

// When a write command is seen on the memory interface, generate a 
// latched signal that is asserted until a read command is presented again.
// This signal along with the dqs signal is used to read the fifo and
// the actual data written into the fifo is compared against the user 
// submitted data.

always @ (posedge user_clk or negedge rst_n) begin
    if (!rst_n) begin
	wdf_wr_addr                  <= 0;
	mem_wr_cmd_lat               <= 0;
	datain_valid_d               <= 0;
    end

    else begin
        datain_valid_d               <= datain_valid;
	if (datain_valid_d) begin
	    wdf_wr_addr              <= wdf_wr_addr + 1;
	end

        `ifdef DDR2_MODE
          `ifdef GATE_SIM
	     mem_wr_cmd_lat           <= (mem_wr_cmd_5d | mem_wr_cmd_lat) &
					~(mem_rd_cmd_4d);
          `else
	     mem_wr_cmd_lat           <= (mem_wr_cmd_5d | mem_wr_cmd_lat) &
					~(mem_rd_cmd_4d);
          `endif
	`else
	    mem_wr_cmd_lat           <= (mem_wr_cmd | mem_wr_cmd_lat) &
					~(mem_rd_cmd);
	`endif

	case (wdf_wr_addr)
            4'd0 : wr_data_fifo[0]   <= {dmsel,datain};
            4'd1 : wr_data_fifo[1]   <= {dmsel,datain};
            4'd2 : wr_data_fifo[2]   <= {dmsel,datain};
            4'd3 : wr_data_fifo[3]   <= {dmsel,datain};
            4'd4 : wr_data_fifo[4]   <= {dmsel,datain};
            4'd5 : wr_data_fifo[5]   <= {dmsel,datain};
            4'd6 : wr_data_fifo[6]   <= {dmsel,datain};
            4'd7 : wr_data_fifo[7]   <= {dmsel,datain};
            4'd8 : wr_data_fifo[8]   <= {dmsel,datain};
            4'd9 : wr_data_fifo[9]   <= {dmsel,datain};
            4'd10 : wr_data_fifo[10] <= {dmsel,datain};
            4'd11 : wr_data_fifo[11] <= {dmsel,datain};
            4'd12 : wr_data_fifo[12] <= {dmsel,datain};
            4'd13 : wr_data_fifo[13] <= {dmsel,datain};
            4'd14 : wr_data_fifo[14] <= {dmsel,datain};
            4'd15 : wr_data_fifo[15] <= {dmsel,datain};
	endcase
    end
end

always @ (posedge ddr_dqs_modified or negedge rst_n) begin
    if (!rst_n) begin
	data_posedge                 <= 72'b0;
	mask_posedge                 <= 9'b0;
    end
    else begin
	data_posedge                 <= ddr_dq;
	mask_posedge                 <= ddr_dqm;
    end
end    

always @ (negedge ddr_dqs_modified or negedge rst_n) begin
    if (!rst_n) begin
	wdf_rd_addr                  <= 0;
    end
    else begin
	if (mem_wr_cmd_lat) begin
	    wdf_rd_addr              <= wdf_rd_addr + 1;
            `ifdef DIS_WR_DT_CMP
            `else
              `ifdef DUMMY_LOGIC
	       `ifdef DATA_SIZE_8
	           if ({wr_data_compare[7:0],wr_data_compare[7:0]}  != {ddr_dq[7:0], data_posedge[7:0]}) begin
		       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq[7:0], data_posedge[7:0]}, {wr_data_compare[7:0],wr_data_compare[7:0]});
	           end
	           if (wr_dm_compare[1:0] != {ddr_dqm[0], mask_posedge[0]}) begin
	   	       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[0], mask_posedge[0]}, wr_dm_compare);
	           //if ({wr_dm_compare[0],wr_dm_compare[0]}  != {ddr_dqm[0], mask_posedge[0]}) begin
	   	   //    $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[0], mask_posedge[0]}, {wr_dm_compare[0],wr_dm_compare[0]);
	           end
	       `endif

	       `ifdef DATA_SIZE_16
	           if ({wr_data_compare[15:0], wr_data_compare[15:0]}  != {ddr_dq[15:0], data_posedge[15:0]}) begin
		       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq[15:0], data_posedge[15:0]}, {wr_data_compare[15:0], wr_data_compare[15:0]});
	           end
	           if (wr_dm_compare[3:0] != {ddr_dqm[1:0], mask_posedge[1:0]}) begin
		       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[1:0], mask_posedge[1:0]}, wr_dm_compare[3:0]);
	           //if ({wr_dm_compare[1:0],wr_dm_compare[1:0]}  != {ddr_dqm[1:0], mask_posedge[1:0]}) begin
		   //    $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[1:0], mask_posedge[1:0]}, {wr_dm_compare[1:0],wr_dm_compare[1:0]});
	           end
	       `endif

	       `ifdef DATA_SIZE_32
	           if ({wr_data_compare[31:0],wr_data_compare[31:0]}  != {ddr_dq[31:0], data_posedge[31:0]}) begin
		       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq[31:0], data_posedge[31:0]}, {wr_data_compare[31:0],wr_data_compare[31:0]});
	           end
	           if (wr_dm_compare[7:0] != {ddr_dqm[3:0], mask_posedge[3:0]}) begin
		       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[3:0], mask_posedge[3:0]}, wr_dm_compare[7:0]);
	           //if ({wr_dm_compare[3:0], wr_dm_compare[3:0]} != {ddr_dqm[3:0], mask_posedge[3:0]}) begin
		   //    $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[3:0], mask_posedge[3:0]}, {wr_dm_compare[3:0], wr_dm_compare[3:0]});
	           end
	       `endif
	       `ifdef DATA_SIZE_64
	           if ({wr_data_compare[63:0],wr_data_compare[63:0]}  != {ddr_dq[63:0], data_posedge[63:0]}) begin
	      	       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq[63:0], data_posedge[63:0]}, {wr_data_compare[63:0],wr_data_compare[63:0]});
	           end
	           if (wr_dm_compare[15:0] != {ddr_dqm[7:0], mask_posedge[7:0]}) begin
		       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[7:0], mask_posedge[7:0]}, wr_dm_compare[15:0]);
	           //if ({wr_dm_compare[7:0],wr_dm_compare[7:0]}  != {ddr_dqm[7:0], mask_posedge[7:0]}) begin
		   //    $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[7:0], mask_posedge[7:0]}, {wr_dm_compare[7:0],wr_dm_compare[7:0]});
	           end
	       `endif

	       `ifdef DATA_SIZE_72
	           if ({wr_data_compare[71:0],wr_data_compare[71:0]}  != {ddr_dq, data_posedge}) begin
	      	       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq, data_posedge}, {wr_data_compare[71:0],wr_data_compare[71:0]});
	           end
	           if (wr_dm_compare != {ddr_dqm, mask_posedge}) begin
		       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm, mask_posedge}, wr_dm_compare);
	           //if ({wr_dm_compare[8:0],wr_dm_compare[8:0]}  != {ddr_dqm, mask_posedge}) begin
		   //    $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm, mask_posedge}, {wr_dm_compare[8:0],wr_dm_compare[8:0]});
	           end
	       `endif

              `else 
	       `ifdef DATA_SIZE_8
	           if (wr_data_compare[15:0] != {ddr_dq[7:0], data_posedge[7:0]}) begin
		       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq[7:0], data_posedge[7:0]}, wr_data_compare);
	           end
	           if (wr_dm_compare[1:0] != {ddr_dqm[0], mask_posedge[0]}) begin
	   	       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[0], mask_posedge[0]}, wr_dm_compare);
	           end
	       `endif

	       `ifdef DATA_SIZE_16
	           if (wr_data_compare[31:0] != {ddr_dq[15:0], data_posedge[15:0]}) begin
		       $display("MON ERROR: At time %0t, data written into memory is %h, Expected data is %h\n",$time, {ddr_dq[15:0], data_posedge[15:0]}, wr_data_compare[31:0]);
	           end
	           if (wr_dm_compare[3:0] != {ddr_dqm[1:0], mask_posedge[1:0]}) begin
		       $display("MON ERROR: At time %0t, Data Mask to memory is %h, Expected data Mask is %h\n",$time, {ddr_dqm[1:0], mask_posedge[1:0]}, wr_dm_compare[3:0]);
	           end
	       `endif

	       `ifdef DATA_SIZE_32
	           if (wr_data_compare[63:0] != {ddr_dq[31:0], data_posedge[31:0]}) begin
		       $display("MON ERROR: At time %0t, data wri