monitor.v

DDR2 的控制器

		7'b1110_101 : mem_row_addr[5] = ddr_ad;
		7'b1110_110 : mem_row_addr[6] = ddr_ad;
		7'b1110_111 : mem_row_addr[7] = ddr_ad;

		7'b1101_000 : mem_row_addr[8] = ddr_ad;
		7'b1101_001 : mem_row_addr[9] = ddr_ad;
		7'b1101_010 : mem_row_addr[10] = ddr_ad;
		7'b1101_011 : mem_row_addr[11] = ddr_ad;
		7'b1101_100 : mem_row_addr[12] = ddr_ad;
		7'b1101_101 : mem_row_addr[13] = ddr_ad;
		7'b1101_110 : mem_row_addr[14] = ddr_ad;
		7'b1101_111 : mem_row_addr[15] = ddr_ad;

		7'b1011_000 : mem_row_addr[16] = ddr_ad;
		7'b1011_001 : mem_row_addr[17] = ddr_ad;
		7'b1011_010 : mem_row_addr[18] = ddr_ad;
		7'b1011_011 : mem_row_addr[19] = ddr_ad;
		7'b1011_101 : mem_row_addr[21] = ddr_ad;
		7'b1011_110 : mem_row_addr[22] = ddr_ad;
		7'b1011_111 : mem_row_addr[23] = ddr_ad;

		7'b0111_000 : mem_row_addr[24] = ddr_ad;
		7'b0111_001 : mem_row_addr[25] = ddr_ad;
		7'b0111_010 : mem_row_addr[26] = ddr_ad;
		7'b0111_011 : mem_row_addr[27] = ddr_ad;
		7'b0111_100 : mem_row_addr[28] = ddr_ad;
		7'b0111_101 : mem_row_addr[29] = ddr_ad;
		7'b0111_110 : mem_row_addr[30] = ddr_ad;
		7'b0111_111 : mem_row_addr[31] = ddr_ad;
	    endcase
        `else 
	    case ({ddr_cs_n,ddr_ba})
		10'b11111110_00 : mem_row_addr[0] = ddr_ad;
		10'b11111110_01 : mem_row_addr[1] = ddr_ad;
		10'b11111110_10 : mem_row_addr[2] = ddr_ad;
		10'b11111110_11 : mem_row_addr[3] = ddr_ad;

		10'b11111101_00 : mem_row_addr[4] = ddr_ad;
		10'b11111101_01 : mem_row_addr[5] = ddr_ad;
		10'b11111101_10 : mem_row_addr[6] = ddr_ad;
		10'b11111101_11 : mem_row_addr[7] = ddr_ad;

		10'b11111011_00 : mem_row_addr[8] = ddr_ad;
		10'b11111011_01 : mem_row_addr[9] = ddr_ad;
		10'b11111011_10 : mem_row_addr[10] = ddr_ad;
		10'b11111011_11 : mem_row_addr[11] = ddr_ad;

		10'b11110111_00 : mem_row_addr[12] = ddr_ad;
		10'b11110111_01 : mem_row_addr[13] = ddr_ad;
		10'b11110111_10 : mem_row_addr[14] = ddr_ad;
		10'b11110111_11 : mem_row_addr[15] = ddr_ad;

		10'b11101111_00 : mem_row_addr[16] = ddr_ad;
		10'b11101111_01 : mem_row_addr[17] = ddr_ad;
		10'b11101111_10 : mem_row_addr[18] = ddr_ad;
		10'b11101111_11 : mem_row_addr[19] = ddr_ad;

		10'b11011111_00 : mem_row_addr[20] = ddr_ad;
		10'b11011111_01 : mem_row_addr[21] = ddr_ad;
		10'b11011111_10 : mem_row_addr[22] = ddr_ad;
		10'b11011111_11 : mem_row_addr[23] = ddr_ad;

		10'b10111111_00 : mem_row_addr[24] = ddr_ad;
		10'b10111111_01 : mem_row_addr[25] = ddr_ad;
		10'b10111111_10 : mem_row_addr[26] = ddr_ad;
		10'b10111111_11 : mem_row_addr[27] = ddr_ad;

		10'b01111111_00 : mem_row_addr[28] = ddr_ad;
		10'b01111111_01 : mem_row_addr[29] = ddr_ad;
		10'b01111111_10 : mem_row_addr[30] = ddr_ad;
		10'b01111111_11 : mem_row_addr[31] = ddr_ad;
	    endcase
       `endif
            `ifdef NO_DEBUG
            `else
	       $display ("MON INFO: At time %0t, Row addr is %0h\n",$time, ddr_ad);
            `endif
	end

	if (mem_burst_cnt == 0)
	    burst_cycle   <= 0;

	`ifdef ECP_20_ONLY
	    if (mem_rd_cmd_3d_new || mem_wr_cmd_3d) begin
	`else
	    if (mem_rd_cmd_d || mem_wr_cmd_d) begin
	`endif
	    // To compare the column address, it is imperative to know if the
	    // current cycle is the only cycle in the burst or the last cycle
	    // of a multiple burst.  If burst_cycle is high, then the cycle is
	    // a part of a multiple burst.

	    if (orig_mem_burst_cnt == 1 || burst_cycle == 1) begin     
	    // not a burst cycle, or first of the burst cycle
		`ifdef COL_WIDTH_GT_10
		    if (((fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0001)) && (fifo_out_col != {ddr_ad_d[`ROW_WIDTH-1:11],ddr_ad_d[9:0]}))
		`else
		    if (((fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0001)) && (fifo_out_col != ddr_ad_d[`COL_WIDTH-1:0]))
		`endif

		    $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, fifo_out_col, ddr_ad_d);


		// Write / Read with auto precharge
		`ifdef COL_WIDTH_GT_10
                        // Since the memory has a col width of 11, the fifo_out_col
			// is truncated appropriately.

		    else if (((fifo_out_cmd == 4'b0011) || (fifo_out_cmd == 4'b0100)) && ({fifo_out_col [10], 1'b1, fifo_out_col[9:0]} != ddr_ad_d))

		        $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, {fifo_out_col [10], 1'b1,fifo_out_col[9:0]}, ddr_ad_d);
		`endif

		`ifdef COL_WIDTH_LT_10
		    else if (((fifo_out_cmd == 4'b0011) || (fifo_out_cmd == 4'b0100)) && ({1'b1,{10-`COL_WIDTH{1'b0}},fifo_out_col[`COL_WIDTH-1:0]} != ddr_ad_d))
		        $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, {1'b1,{10-`COL_WIDTH{1'b0}},fifo_out_col[`COL_WIDTH-1:0]}, ddr_ad_d);
		`endif

		`ifdef COL_WIDTH_EQ_10
		    else if (((fifo_out_cmd == 4'b0011) || (fifo_out_cmd == 4'b0100)) && ({1'b1,fifo_out_col[9:0]} != ddr_ad_d))
		        $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, {1'b1,fifo_out_col[`COL_WIDTH-1:0]}, ddr_ad_d);
		`endif

	    end
	    else begin
		`ifdef COL_WIDTH_GT_10
		    if ((fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0001)) begin
		        if ({ddr_ad_d[`ROW_WIDTH-1:11],ddr_ad_d[9:0]} != lt_10_exp_col_addr)
		            $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, lt_10_exp_col_addr, ddr_ad_d);
		    end
		`endif

		`ifdef COL_WIDTH_LT_10
		    if ((fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0001)) begin
		        if (ddr_ad_d[`COL_WIDTH-1:0] != lt_10_exp_col_addr)
		            $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, lt_10_exp_col_addr, ddr_ad_d);
		    end
		`endif

		`ifdef COL_WIDTH_EQ_10
		    if ((fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0001)) begin
		        if (ddr_ad_d[`COL_WIDTH-1:0] != lt_10_exp_col_addr)
		            $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, (fifo_out_col + ((burst_cycle-1)*int_burst_len)), ddr_ad_d);
		    end
		`endif

		`ifdef COL_WIDTH_GT_10
		    else if ((fifo_out_cmd == 4'b0100) || (fifo_out_cmd == 4'b0011)) begin
		        if (ddr_ad_d != ({1'b1,fifo_out_col[9:0]} + ((burst_cycle-1)*int_burst_len)))
		            $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, ({1'b1,fifo_out_col[9:0]} + ((burst_cycle-1)*int_burst_len)), ddr_ad_d);
		    end
		`endif

		`ifdef COL_WIDTH_LT_10
		    else if ((fifo_out_cmd == 4'b0100) || (fifo_out_cmd == 4'b0011)) begin
		        if (ddr_ad_d != ({1'b1,{10-`COL_WIDTH{1'b0}},fifo_out_col[`COL_WIDTH-1:0]} + ((burst_cycle-1)*int_burst_len)))
		            $display ("MON ERROR: Col address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, ({1'b1,{10-`COL_WIDTH{1'b0}},fifo_out_col[`COL_WIDTH-1:0]} + ((burst_cycle-1)*int_burst_len)), ddr_ad_d);
		    end
		`endif
	    end
	end

	`ifdef ECP_20_ONLY
	    if (mem_rd_cmd_3d_new || mem_wr_cmd_3d) begin
	`else
	    if (mem_rd_cmd_d || mem_wr_cmd_d) begin
	`endif
            `ifdef NO_DEBUG
            `else
	       $display ("MON INFO: At time %0t, Col addr is %0h\n",$time, ddr_ad_d);
            `endif

            `ifdef INT_BANK_8
	    case ({ddr_cs_n_d,ddr_ba_d})
		7'b1110_000 : mem_row_addr_out = mem_row_addr[0];
		7'b1110_001 : mem_row_addr_out = mem_row_addr[1];
		7'b1110_010 : mem_row_addr_out = mem_row_addr[2];
		7'b1110_011 : mem_row_addr_out = mem_row_addr[3];
		7'b1110_100 : mem_row_addr_out = mem_row_addr[4];
		7'b1110_101 : mem_row_addr_out = mem_row_addr[5];
		7'b1110_110 : mem_row_addr_out = mem_row_addr[6];
		7'b1110_111 : mem_row_addr_out = mem_row_addr[7];

		7'b1101_000 : mem_row_addr_out = mem_row_addr[8];
		7'b1101_001 : mem_row_addr_out = mem_row_addr[9];
		7'b1101_010 : mem_row_addr_out = mem_row_addr[10];
		7'b1101_011 : mem_row_addr_out = mem_row_addr[11];
		7'b1101_100 : mem_row_addr_out = mem_row_addr[12];
		7'b1101_101 : mem_row_addr_out = mem_row_addr[13];
		7'b1101_110 : mem_row_addr_out = mem_row_addr[14];
		7'b1101_111 : mem_row_addr_out = mem_row_addr[15];

		7'b1011_000 : mem_row_addr_out = mem_row_addr[16];
		7'b1011_001 : mem_row_addr_out = mem_row_addr[17];
		7'b1011_010 : mem_row_addr_out = mem_row_addr[18];
		7'b1011_011 : mem_row_addr_out = mem_row_addr[19];
		7'b1011_100 : mem_row_addr_out = mem_row_addr[20];
		7'b1011_101 : mem_row_addr_out = mem_row_addr[21];
		7'b1011_110 : mem_row_addr_out = mem_row_addr[22];
		7'b1011_111 : mem_row_addr_out = mem_row_addr[23];

		7'b0111_000 : mem_row_addr_out = mem_row_addr[24];
		7'b0111_001 : mem_row_addr_out = mem_row_addr[25];
		7'b0111_010 : mem_row_addr_out = mem_row_addr[26];
		7'b0111_011 : mem_row_addr_out = mem_row_addr[27];
		7'b0111_100 : mem_row_addr_out = mem_row_addr[28];
		7'b0111_101 : mem_row_addr_out = mem_row_addr[29];
		7'b0111_110 : mem_row_addr_out = mem_row_addr[30];
		7'b0111_111 : mem_row_addr_out = mem_row_addr[31];
	    endcase
           `else
	    case ({ddr_cs_n_d,ddr_ba_d})
		10'b11111110_00 : mem_row_addr_out = mem_row_addr[0];
		10'b11111110_01 : mem_row_addr_out = mem_row_addr[1];
		10'b11111110_10 : mem_row_addr_out = mem_row_addr[2];
		10'b11111110_11 : mem_row_addr_out = mem_row_addr[3];

		10'b11111101_00 : mem_row_addr_out = mem_row_addr[4];
		10'b11111101_01 : mem_row_addr_out = mem_row_addr[5];
		10'b11111101_10 : mem_row_addr_out = mem_row_addr[6];
		10'b11111101_11 : mem_row_addr_out = mem_row_addr[7];

		10'b11111011_00 : mem_row_addr_out = mem_row_addr[8];
		10'b11111011_01 : mem_row_addr_out = mem_row_addr[9];
		10'b11111011_10 : mem_row_addr_out = mem_row_addr[10];
		10'b11111011_11 : mem_row_addr_out = mem_row_addr[11];

		10'b11110111_00 : mem_row_addr_out = mem_row_addr[12];
		10'b11110111_01 : mem_row_addr_out = mem_row_addr[13];
		10'b11110111_10 : mem_row_addr_out = mem_row_addr[14];
		10'b11110111_11 : mem_row_addr_out = mem_row_addr[15];

		10'b11101111_00 : mem_row_addr_out = mem_row_addr[16];
		10'b11101111_01 : mem_row_addr_out = mem_row_addr[17];
		10'b11101111_10 : mem_row_addr_out = mem_row_addr[18];
		10'b11101111_11 : mem_row_addr_out = mem_row_addr[19];

		10'b11011111_00 : mem_row_addr_out = mem_row_addr[20];
		10'b11011111_01 : mem_row_addr_out = mem_row_addr[21];
		10'b11011111_10 : mem_row_addr_out = mem_row_addr[22];
		10'b11011111_11 : mem_row_addr_out = mem_row_addr[23];

		10'b10111111_00 : mem_row_addr_out = mem_row_addr[24];
		10'b10111111_01 : mem_row_addr_out = mem_row_addr[25];
		10'b10111111_10 : mem_row_addr_out = mem_row_addr[26];
		10'b10111111_11 : mem_row_addr_out = mem_row_addr[27];

		10'b01111111_00 : mem_row_addr_out = mem_row_addr[28];
		10'b01111111_01 : mem_row_addr_out = mem_row_addr[29];
		10'b01111111_10 : mem_row_addr_out = mem_row_addr[30];
		10'b01111111_11 : mem_row_addr_out = mem_row_addr[31];
	    endcase
            `endif

	    if (fifo_out_row != mem_row_addr_out)
		$display ("MON ERROR: Row address mismatch at %0t, Expected %0h, Actual, %0h\n", $time, fifo_out_row, mem_row_addr_out);
	end

        `ifdef ECP_20_ONLY
            if ((mem_rd_cmd_2d & ~non_cs_rd) || mem_wr_cmd_2d) begin
        `else
            if (mem_rd_cmd || mem_wr_cmd) begin
        `endif
	    // decrement the burst counter after every read or write cycle

	    // This logic sets a bit indicating that the following read/write 
	    // commands are a part of the burst.  This is used to compare the 
	    // addresses

	    if (mem_burst_cnt != 5'b0) begin
		mem_burst_cnt = mem_burst_cnt - 1;
		burst_cycle   = burst_cycle + 1;
	    end
	    else begin
		mem_burst_cnt = 0;
		burst_cycle   = 0;
	    end
	end

	//if (fifo_rd)
	    //mem_burst_cnt = orig_mem_burst_cnt;

	casex ({mem_bt_cmd, mem_sref_cmd, mem_pd_cmd, mem_lmr_cmd,
	      mem_aref_cmd, mem_act_cmd, mem_pre_cmd,
	      mem_rd_cmd, mem_wr_cmd, mem_nop_cmd})

	    10'b1000000000,
	    10'b0100000000,
	    10'bxx1xxxxxxx,
	    10'b0001000000,
	    10'b0000100000,
	    10'b0000010000,
	    10'b0000001000,
	    10'b0000000100,
	    10'b0000000010,
	    10'b0000000001 : begin
	    end
	    default      : $display ("MON ERROR: Invalid command found on the DDR interface at %0t\n",$time);
	endcase

	if (mem_sref_cmd || mem_lmr_cmd || (mem_pre_cmd && ddr_ad[10])) begin
	    if (ddr_cs_n != 8'h00)
	        $display ("MON ERROR: Chip selects not 8'h00 at time %0t\n",$time);
	end

	if (mem_rd_cmd || mem_wr_cmd || mem_act_cmd || mem_pre_cmd) begin
	    
	    `ifdef CS_WIDTH_8
	        case (ddr_cs_n)
		    8'b11111110,
		    8'b11111101,
		    8'b11111011,
		    8'b11110111,
		    8'b11101111,
		    8'b11011111,
		    8'b10111111,
		    8'b01111111 : begin
		    end
		    default : begin
		        if (mem_pre_cmd && ~ddr_ad[10])
                            $display ("MON ERROR: Illegal chip select at time %0t\n",$time);
                    end
	       endcase
	    `endif

	    `ifdef CS_WIDTH_4
	        case (ddr_cs_n)
		    4'b1110,
		    4'b1101,
		    4'b1011,
		    4'b0111 : begin
		    end
		    default : begin
		        if (mem_pre_cmd && ~ddr_ad[10])
                            $display ("MON ERROR: Illegal chip select at time %0t\n",$time);
                    end
	       endcase
	    `endif

	    `ifdef CS_WIDTH_2
	        case (ddr_cs_n)
		    2'b10,
		    2'b01 : begin
		    end
		    default : begin
		        if (mem_pre_cmd && ~ddr_ad[10])
                            $display ("MON ERROR: Illegal chip select at time %0t\n",$time);