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6'd18 : mem_bnk[18] <= {burst_cnt,cmd, addr};
6'd19 : mem_bnk[19] <= {burst_cnt,cmd, addr};
6'd20 : mem_bnk[20] <= {burst_cnt,cmd, addr};
6'd21 : mem_bnk[21] <= {burst_cnt,cmd, addr};
6'd22 : mem_bnk[22] <= {burst_cnt,cmd, addr};
6'd23 : mem_bnk[23] <= {burst_cnt,cmd, addr};
6'd24 : mem_bnk[24] <= {burst_cnt,cmd, addr};
6'd25 : mem_bnk[25] <= {burst_cnt,cmd, addr};
6'd26 : mem_bnk[26] <= {burst_cnt,cmd, addr};
6'd27 : mem_bnk[27] <= {burst_cnt,cmd, addr};
6'd28 : mem_bnk[28] <= {burst_cnt,cmd, addr};
6'd29 : mem_bnk[29] <= {burst_cnt,cmd, addr};
6'd30 : mem_bnk[30] <= {burst_cnt,cmd, addr};
6'd31 : mem_bnk[31] <= {burst_cnt,cmd, addr};
6'd32 : mem_bnk[32] <= {burst_cnt,cmd, addr};
6'd33 : mem_bnk[33] <= {burst_cnt,cmd, addr};
6'd34 : mem_bnk[34] <= {burst_cnt,cmd, addr};
6'd35 : mem_bnk[35] <= {burst_cnt,cmd, addr};
6'd36 : mem_bnk[36] <= {burst_cnt,cmd, addr};
6'd37 : mem_bnk[37] <= {burst_cnt,cmd, addr};
6'd38 : mem_bnk[38] <= {burst_cnt,cmd, addr};
6'd39 : mem_bnk[39] <= {burst_cnt,cmd, addr};
6'd40 : mem_bnk[40] <= {burst_cnt,cmd, addr};
6'd41 : mem_bnk[41] <= {burst_cnt,cmd, addr};
6'd42 : mem_bnk[42] <= {burst_cnt,cmd, addr};
6'd43 : mem_bnk[43] <= {burst_cnt,cmd, addr};
6'd44 : mem_bnk[44] <= {burst_cnt,cmd, addr};
6'd45 : mem_bnk[45] <= {burst_cnt,cmd, addr};
6'd46 : mem_bnk[46] <= {burst_cnt,cmd, addr};
6'd47 : mem_bnk[47] <= {burst_cnt,cmd, addr};
6'd48 : mem_bnk[48] <= {burst_cnt,cmd, addr};
6'd49 : mem_bnk[49] <= {burst_cnt,cmd, addr};
6'd50 : mem_bnk[50] <= {burst_cnt,cmd, addr};
6'd51 : mem_bnk[51] <= {burst_cnt,cmd, addr};
6'd52 : mem_bnk[52] <= {burst_cnt,cmd, addr};
6'd53 : mem_bnk[53] <= {burst_cnt,cmd, addr};
6'd54 : mem_bnk[54] <= {burst_cnt,cmd, addr};
6'd55 : mem_bnk[55] <= {burst_cnt,cmd, addr};
6'd56 : mem_bnk[56] <= {burst_cnt,cmd, addr};
6'd57 : mem_bnk[57] <= {burst_cnt,cmd, addr};
6'd58 : mem_bnk[58] <= {burst_cnt,cmd, addr};
6'd59 : mem_bnk[59] <= {burst_cnt,cmd, addr};
6'd60 : mem_bnk[60] <= {burst_cnt,cmd, addr};
6'd61 : mem_bnk[61] <= {burst_cnt,cmd, addr};
6'd62 : mem_bnk[62] <= {burst_cnt,cmd, addr};
6'd63 : mem_bnk[63] <= {burst_cnt,cmd, addr};
endcase
wr_addr <= wr_addr + 1;
end // if (cmd_rdy && cmd_valid) begin
end
end // always @ (negedge clk or negedge rst_n) begin
// The FIFO at the memory interface is read whenever a read, write,
// self ref, pdown or load mr command is received. For burst reads or writes,
// the FIFO is read only once at the start of the burst.
// self refresh: cke=0, cs=0, ras=0, cas=0, we=1
// powerdown: cke=0
// lmr: cs=0, ras=0, cas=0, we=0
// act: cs=0, ras=0, cas=1, we=1
// pre: cs=0, ras=0, cas=1, we=0
// nop: cs=0, ras=1, cas=1, we=1
assign mem_sref_cmd = ~(&ddr_cs_n) & ~ddr_cke &
~ddr_ras_n & ~ddr_cas_n & ddr_we_n;
assign mem_pd_cmd = ~(&ddr_cs_n) & ddr_ras_n & ddr_cas_n & ddr_we_n & ~ddr_cke;
assign mem_lmr_cmd = ~(&ddr_cs_n) & ~ddr_ras_n & ~ddr_cas_n & ~ddr_we_n;
assign mem_act_cmd = ~(&ddr_cs_n) & ~ddr_ras_n & ddr_cas_n & ddr_we_n;
assign mem_pre_cmd = ~(&ddr_cs_n) & ~ddr_ras_n & ddr_cas_n & ~ddr_we_n;
assign mem_nop_cmd = (~(&ddr_cs_n) & ddr_ras_n & ddr_cas_n & ddr_we_n) |
&ddr_cs_n;
assign mem_bt_cmd = ~(&ddr_cs_n) & ddr_ras_n & ddr_cas_n & ~ddr_we_n;
// The fifo_rd is not issued for the extra read cycle for EC devices.
`ifdef ECP_20_ONLY
assign fifo_rd = (mem_burst_cnt == 0) & ~init_start &
((mem_rd_cmd_2d & ~non_cs_rd) | mem_wr_cmd_2d | mem_lmr_cmd |
(mem_pd_cmd & ~mem_pd_cmd_d) |
(mem_sref_cmd & ~mem_sref_cmd_d));
`else
`ifdef DDR2_MODE
assign fifo_rd = (mem_burst_cnt == 0) & ~init_start_d3 &
(mem_rd_cmd | mem_wr_cmd | mem_lmr_cmd |
(mem_pd_cmd & ~mem_pd_cmd_d) |
(mem_sref_cmd & ~mem_sref_cmd_d));
`else
assign fifo_rd = (mem_burst_cnt == 0) & ~init_start &
(mem_rd_cmd | mem_wr_cmd | mem_lmr_cmd |
(mem_pd_cmd & ~mem_pd_cmd_d) |
(mem_sref_cmd & ~mem_sref_cmd_d));
`endif
`endif
assign fifo_out_cmd = fifo_out[`ADDR_WIDTH+3:`ADDR_WIDTH];
assign fifo_out_row = fifo_out[`ADDR_WIDTH-1:`BSIZE+`COL_WIDTH];
assign fifo_out_col = fifo_out[`COL_WIDTH-1:0];
assign fifo_out_bank = fifo_out[`COL_WIDTH+`BSIZE-1:`COL_WIDTH];
reg [`COL_WIDTH-1:0] lt_10_exp_col_addr;
// compute the expected column address.
always @ (fifo_out_col or burst_cycle or int_burst_len) begin
lt_10_exp_col_addr = fifo_out_col + ((burst_cycle-1)*int_burst_len);
end
////////////////////////////////////////////////////////////////////
// Sample the commands on the sdram memory interface
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
rd_addr <= 6'b0;
mem_pd_cmd_d <= 1'b0;
mem_sref_cmd_d <= 1'b0;
fifo_rd_d <= 1'b0;
mem_burst_cnt = 5'b0;
mem_rd_cmd_d <= 1'b0;
mem_rd_cmd_2d <= 1'b0;
mem_rd_cmd_3d <= 1'b0;
mem_rd_cmd_4d <= 1'b0;
mem_rd_cmd_3d_new <= 1'b0;
mem_wr_cmd_d <= 1'b0;
mem_wr_cmd_2d <= 1'b0;
mem_wr_cmd_3d <= 1'b0;
mem_wr_cmd_4d <= 1'b0;
mem_wr_cmd_5d <= 1'b0;
mem_lmr_cmd_d <= 1'b0;
burst_cycle <= 0;
flop_ddr_ad <= 0;
flop2_ddr_ad <= 0;
flop3_ddr_ad <= 0;
flop_ddr_cs_n <= 8'hff;
flop2_ddr_cs_n <= 8'hff;
flop3_ddr_cs_n <= 8'hff;
flop_ddr_ba <= 3'd0;
flop2_ddr_ba <= 3'd0;
flop3_ddr_ba <= 3'd0;
end
else begin
flop_ddr_ad <= ddr_ad;
flop2_ddr_ad <= flop_ddr_ad;
flop3_ddr_ad <= flop2_ddr_ad;
flop_ddr_cs_n <= ddr_cs_n;
flop2_ddr_cs_n <= flop_ddr_cs_n;
flop3_ddr_cs_n <= flop2_ddr_cs_n;
flop_ddr_ba <= ddr_ba;
flop2_ddr_ba <= flop_ddr_ba;
flop3_ddr_ba <= flop2_ddr_ba;
mem_pd_cmd_d <= mem_pd_cmd;
mem_sref_cmd_d <= mem_sref_cmd;
fifo_rd_d <= fifo_rd;
mem_rd_cmd_d <= mem_rd_cmd;
mem_rd_cmd_2d <= mem_rd_cmd_d;
mem_rd_cmd_3d <= mem_rd_cmd_2d;
mem_rd_cmd_4d <= mem_rd_cmd_3d;
mem_rd_cmd_3d_new <= mem_rd_cmd_2d & fifo_rd;
mem_wr_cmd_d <= mem_wr_cmd;
mem_lmr_cmd_d <= mem_lmr_cmd;
mem_wr_cmd_2d <= mem_wr_cmd_d;
mem_wr_cmd_3d <= mem_wr_cmd_2d;
mem_wr_cmd_4d <= mem_wr_cmd_3d;
mem_wr_cmd_5d <= mem_wr_cmd_4d;
if (fifo_rd) begin
rd_addr <= rd_addr + 1;
// blocking statement is used intentionally so that comparison
// can happen straight away.
case (rd_addr)
6'd0 : fifo_out = mem_bnk[0];
6'd1 : fifo_out = mem_bnk[1];
6'd2 : fifo_out = mem_bnk[2];
6'd3 : fifo_out = mem_bnk[3];
6'd4 : fifo_out = mem_bnk[4];
6'd5 : fifo_out = mem_bnk[5];
6'd6 : fifo_out = mem_bnk[6];
6'd7 : fifo_out = mem_bnk[7];
6'd8 : fifo_out = mem_bnk[8];
6'd9 : fifo_out = mem_bnk[9];
6'd10 : fifo_out = mem_bnk[10];
6'd11 : fifo_out = mem_bnk[11];
6'd12 : fifo_out = mem_bnk[12];
6'd13 : fifo_out = mem_bnk[13];
6'd14 : fifo_out = mem_bnk[14];
6'd15 : fifo_out = mem_bnk[15];
6'd16 : fifo_out = mem_bnk[16];
6'd17 : fifo_out = mem_bnk[17];
6'd18 : fifo_out = mem_bnk[18];
6'd19 : fifo_out = mem_bnk[19];
6'd20 : fifo_out = mem_bnk[20];
6'd21 : fifo_out = mem_bnk[21];
6'd22 : fifo_out = mem_bnk[22];
6'd23 : fifo_out = mem_bnk[23];
6'd24 : fifo_out = mem_bnk[24];
6'd25 : fifo_out = mem_bnk[25];
6'd26 : fifo_out = mem_bnk[26];
6'd27 : fifo_out = mem_bnk[27];
6'd28 : fifo_out = mem_bnk[28];
6'd29 : fifo_out = mem_bnk[29];
6'd30 : fifo_out = mem_bnk[30];
6'd31 : fifo_out = mem_bnk[31];
6'd32 : fifo_out = mem_bnk[32];
6'd33 : fifo_out = mem_bnk[33];
6'd34 : fifo_out = mem_bnk[34];
6'd35 : fifo_out = mem_bnk[35];
6'd36 : fifo_out = mem_bnk[36];
6'd37 : fifo_out = mem_bnk[37];
6'd38 : fifo_out = mem_bnk[38];
6'd39 : fifo_out = mem_bnk[39];
6'd40 : fifo_out = mem_bnk[40];
6'd41 : fifo_out = mem_bnk[41];
6'd42 : fifo_out = mem_bnk[42];
6'd43 : fifo_out = mem_bnk[43];
6'd44 : fifo_out = mem_bnk[44];
6'd45 : fifo_out = mem_bnk[45];
6'd46 : fifo_out = mem_bnk[46];
6'd47 : fifo_out = mem_bnk[47];
6'd48 : fifo_out = mem_bnk[48];
6'd49 : fifo_out = mem_bnk[49];
6'd50 : fifo_out = mem_bnk[50];
6'd51 : fifo_out = mem_bnk[51];
6'd52 : fifo_out = mem_bnk[52];
6'd53 : fifo_out = mem_bnk[53];
6'd54 : fifo_out = mem_bnk[54];
6'd55 : fifo_out = mem_bnk[55];
6'd56 : fifo_out = mem_bnk[56];
6'd57 : fifo_out = mem_bnk[57];
6'd58 : fifo_out = mem_bnk[58];
6'd59 : fifo_out = mem_bnk[59];
6'd60 : fifo_out = mem_bnk[60];
6'd61 : fifo_out = mem_bnk[61];
6'd62 : fifo_out = mem_bnk[62];
6'd63 : fifo_out = mem_bnk[63];
endcase
`ifdef ECP_20_ONLY
if ((mem_rd_cmd_2d & ~non_cs_rd) || mem_wr_cmd_2d)
`else
if (mem_rd_cmd || mem_wr_cmd)
`endif
mem_burst_cnt = (burst_term === 1'b1 && mem_rd_cmd) ? 3'b0 : fifo_out[`ADDR_WIDTH+8:`ADDR_WIDTH+4];
end
// assign the burst count value to the mem_burst_cnt signal.
orig_mem_burst_cnt = fifo_out[`ADDR_WIDTH+8:`ADDR_WIDTH+4];
// Compare the command presented at the user interface with
// the command seen on the memory interface
// --------------- Read command comparison ---------------------
`ifdef ECP_20_ONLY
if (mem_rd_cmd_3d_new && (
`else
if (mem_rd_cmd_d && (
`endif
(fifo_out_cmd == 4'b0001) || (fifo_out_cmd == 4'b0011))) begin
`ifdef NO_DEBUG
`else
$display ("MON INFO: Read command at time %0t\n",$time);
`endif
end
`ifdef ECP_20_ONLY
if (mem_rd_cmd_3d_new && !(
`else
if (mem_rd_cmd_d && !(
`endif
(fifo_out_cmd == 4'b0001) || (fifo_out_cmd == 4'b0011))) begin
//$display ("MON ERROR: Unexpected Read command at time %0t\n",$time);
end
// --------------- Write command comparison ---------------------
`ifdef ECP_20_ONLY
if (mem_wr_cmd_3d && (
`else
if (mem_wr_cmd_d && (
`endif
(fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0100))) begin
`ifdef NO_DEBUG
`else
$display ("MON INFO: Write command at time %0t\n",$time);
`endif
end
`ifdef ECP_20_ONLY
if (mem_wr_cmd_3d && !(
`else
if (mem_wr_cmd_d && !(
`endif
(fifo_out_cmd == 4'b0010) || (fifo_out_cmd == 4'b0100))) begin
$display ("MON ERROR: Unexpected Write command at time %0t\n",$time);
end
// --------------- LMR command comparison ---------------------
if (mem_lmr_cmd_d && (fifo_out_cmd == 4'b0110)) begin
`ifdef NO_DEBUG
`else
$display ("MON INFO: LMR command at time %0t\n",$time);
`endif
end
if (mem_lmr_cmd_d && (fifo_out_cmd != 4'b0110)) begin
$display ("MON ERROR: Unexpected LMR command at time %0t\n",$time);
end
// --------------- Self Ref command comparison ------------------
if (mem_sref_cmd_d && !mem_sref_cmd_d && (fifo_out_cmd == 4'b0111)) begin
`ifdef NO_DEBUG
`else
$display ("MON INFO: Self Ref command at time %0t\n",$time);
`endif
end
if (mem_sref_cmd_d && !mem_sref_cmd_d && (fifo_out_cmd != 4'b0111)) begin
$display ("MON ERROR: Unexpected Self Ref command at time %0t\n",$time);
end
// --------------- Powerdown command comparison ------------------
if (mem_pd_cmd && !mem_pd_cmd_d && (fifo_out_cmd == 4'b0101)) begin
`ifdef NO_DEBUG
`else
$display ("MON INFO: Powerdown command at time %0t\n",$time);
`endif
end
if (mem_pd_cmd_d && (fifo_out_cmd != 4'b0101)) begin
$display ("MON ERROR: Unexpected Powerdown command at time %0t\n",$time);
end
// Every time an Active command is detected, store the address (row).
// This will be compared with the user provided address when
// the fifo is read upon detecting a read/write command
if (mem_act_cmd) begin
`ifdef INT_BANK_8 // Assuming 4 CS and 8 Banks
case ({ddr_cs_n,ddr_ba})
7'b1110_000 : mem_row_addr[0] = ddr_ad;
7'b1110_001 : mem_row_addr[1] = ddr_ad;
7'b1110_010 : mem_row_addr[2] = ddr_ad;
7'b1110_011 : mem_row_addr[3] = ddr_ad;
7'b1110_100 : mem_row_addr[4] = ddr_ad;
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