📄 test_mem_ctrl.v
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ddr_ras_n <= HIGH;
ddr_ad <= {DDR_ADR_WIDTH{LOW}};
ddr_ba <= 'd0;
end
else begin
# (1000);
ddr_cke <= ddr_cke_tmp[0];
ddr_cs_n <= ddr_cs_n_tmp;
ddr_we_n <= ddr_we_n_tmp;
ddr_cas_n <= ddr_cas_n_tmp;
ddr_ras_n <= ddr_ras_n_tmp;
ddr_ad <= ddr_ad_tmp;
ddr_ba <= ddr_ba_tmp;
end
end
`else
always @ (ddr_ad_tmp or ddr_ba_tmp or ddr_cas_n_tmp
or ddr_cke_tmp or ddr_cs_n_tmp or ddr_ras_n_tmp
or ddr_we_n_tmp) begin
ddr_cke = ddr_cke_tmp[0];
ddr_cs_n = ddr_cs_n_tmp;
ddr_we_n = ddr_we_n_tmp;
ddr_cas_n = ddr_cas_n_tmp;
ddr_ras_n = ddr_ras_n_tmp;
ddr_ad = ddr_ad_tmp;
ddr_ba = ddr_ba_tmp;
end
`endif
// ====================================================================
// Instantiate the memory devices
// ====================================================================
wire dly_ddr_ras_n; // delayed signal to the mem
wire dly_ddr_cas_n; // delayed signal to the mem
wire dly_ddr_we_n; // delayed signal to the mem
wire dly_ddr_cke; // delayed signal to the mem
wire [`CS_WIDTH-1:0] dly_ddr_cs_n; // delayed signal to the mem
wire [`CS_WIDTH-1:0] dly_ddr_odt; // delayed signal to the mem
wire [`ROW_WIDTH-1:0] dly_ddr_ad; // delayed signal to the mem
wire [`BNK_WDTH-1:0] dly_ddr_ba; // delayed signal to the mem
wire [63:0] dly_ddr_dq; // delayed signal to the mem
assign #(`HOLD_DLY) dly_ddr_ras_n = ddr_ras_n;
assign #(`HOLD_DLY) dly_ddr_cas_n = ddr_cas_n;
assign #(`HOLD_DLY) dly_ddr_we_n = ddr_we_n;
assign #(`HOLD_DLY) dly_ddr_cke = ddr_cke;
assign #(`HOLD_DLY) dly_ddr_cs_n = ddr_cs_n;
assign #(`HOLD_DLY) dly_ddr_ad = ddr_ad;
assign #(`HOLD_DLY) dly_ddr_ba = ddr_ba;
assign #(`HOLD_DLY) dly_ddr_dq = ddr_dq_int;
assign #(`HOLD_DLY) dly_ddr_odt = ddr_odt;
initial begin
`ifdef REDUCED_MEM
$display (">>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>");
$display ("INFO: Running in the reduced memory mode, where memory size is reduced from the full mem");
$display ("<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<");
`endif
end
`ifdef DATA_SIZE_72
`ifdef DDR2_MODE
ddr2_db_width_72 U1_ddr2_db_width_72(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_dqs_n (inv_ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_odt (dly_ddr_odt),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`else
mem_db_width_72 U2_mem_db_width_72(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`endif
`endif
`ifdef DATA_SIZE_64
`ifdef DDR2_MODE
ddr2_db_width_64 U1_ddr2_db_width_64(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_dqs_n (inv_ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_odt (dly_ddr_odt),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`else // !`ifdef DDR2_MODE
mem_db_width_64 U1_mem_db_width_64(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`endif
`endif // `ifdef DATA_SIZE_64
`ifdef DATA_SIZE_32
`ifdef DDR2_MODE
ddr2_db_width_32 U1_ddr2_db_width_32(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_dqs_n (inv_ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_odt (dly_ddr_odt),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`else
mem_db_width_32 U1_mem_db_width_32(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`endif
`endif
`ifdef DATA_SIZE_16
`ifdef DDR2_MODE
ddr2_db_width_16 U1_ddr2_db_width_16(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_dqs_n (inv_ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_odt (dly_ddr_odt),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`else
mem_db_width_16 U1_mem_db_width_16(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`endif
`endif
`ifdef DATA_SIZE_8
`ifdef DDR2_MODE
ddr2_db_width_8 U1_ddr2_db_width_8(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_dqs_n (inv_ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_odt (dly_ddr_odt),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`else
mem_db_width_8 U1_mem_db_width_8(
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_ad (dly_ddr_ad),
.ddr_ba (dly_ddr_ba),
.ddr_clk (ddr_clk[0]),
.ddr_clk_n (~ddr_clk[0]),
.ddr_cke (dly_ddr_cke),
.ddr_cs_n (dly_ddr_cs_n),
.ddr_ras_n (dly_ddr_ras_n),
.ddr_cas_n (dly_ddr_cas_n),
.ddr_we_n (dly_ddr_we_n),
.ddr_dqm (ddr_dqm)
);
`endif
`endif
// ====================================================================
// This file has all the tasks used in the tests to generate stimulus on
// the FPGA interface for the DDR memory controller
// ====================================================================
reg dm_toggle; // 0: data mask=0
// 1: random pattern on data mask
initial begin
dm_toggle = 0;
end
// ====================================================================
// Instantiate the protocol monitor
// ====================================================================
reg endoftest;
initial begin
endoftest = 0;
end
`ifdef GATE_SIM
assign ar_burst_en = `AR_BURST_EN;
`else
`define CORE_AR_BURST_EN U1_ddr_sdram_mem_top.U1_ddr_sdram_mem_core.ar_burst_en
assign ar_burst_en = `CORE_AR_BURST_EN;
`endif
`ifdef GATE_SIM
wire user_clk_del;
assign #1587 user_clk_del= clk;
wire [`DATA_WIDTH/8-1:0] ddr_dqs_int_dl;
assign #587 ddr_dqs_int_dl = ddr_dqs_int;
`endif
monitor U1_monitor (
.rst_n (rst_n),
.endoftest (endoftest),
.cmd (cmd_dly),
.cmd_valid (cmd_valid_dly),
.dmsel (dmsel),
.addr (addr),
.datain (datain),
`ifdef BRST_CNT_EN
.burst_cnt (ff_burst_count),
`else
.burst_cnt (5'h1),
`endif
.init_start (init_start),
.init_done (init_done),
.ar_burst_en (ar_burst_en),
.ext_reg_en (ext_reg_en),
.db_size (db_size),
.burst_term (ff_burst_term),
.ddr_cke (ddr_cke),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_ad (ddr_ad),
.ddr_ba (ddr_ba),
.ddr_dqm (ddr_dqm),
.ddr_dq (ddr_dq_int),
.clk (ddr_clk[0]),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
`ifdef GATE_SIM
.ddr_dqs (ddr_dqs_int_dl),
.user_clk (user_clk_del),
`else
.ddr_dqs (ddr_dqs_int),
.user_clk (clk),
`endif
.dataout (usr_data_out),
.cmd_rdy (cmd_rdy),
.dataout_valid (usr_data_out_en),
.datain_valid (datain_valid)
);
// ====================================================================
// Instantiate the ODT watchdog
// ====================================================================
odt_watchdog U1_odt_watchdog (
.mem_clk (ddr_clk[0]),
.rst_n (rst_n),
.ddr_cke (ddr_cke),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_ad (ddr_ad),
.ddr_ba (ddr_ba),
.ddr_dqm (ddr_dqm),
.ddr_dq (ddr_dq_int),
.ddr_dqs (ddr_dqs_int),
.ddr_odt (ddr_odt)
);
// ====================================================================
// Initialize the static parameters
// ====================================================================
initial begin
`ifdef DATA_SIZE_72
`ifdef DDR2_MODE
`else //ddr1 mode
`ifdef SLAYER
db_size = 3'b100;
`else //EC simulation uses old sim model
`ifdef CONFIG3
db_size = 3'b100;
`else
db_size = 3'b100;
`endif
`endif
`endif
`endif
`ifdef DATA_SIZE_64
db_size = 3'b000;
`endif
`ifdef DATA_SIZE_32
db_size = 3'b001;
`endif
`ifdef DATA_SIZE_16
db_size = 3'b010;
`endif
`ifdef DATA_SIZE_8
db_size = 3'b011;
`endif
end
`include "cmd_gen.v"
`include "testcase.v"
endmodule
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