ddr2_eval.jid

DDR2 的控制器

. ddr_sdram_mem_top ..\src\rtl\top\ecp2m\ddr_sdram_mem_top.v d:\ddr2_sdram\ddr_p_eval\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v
U1_ddr_sdram_mem_io_top ddr_sdram_mem_io_top ..\..\models\ecp2m\ddr_sdram_mem_io_top.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\ddr_sdram_mem_io_top.v
U1_ddr_sdram_mem_io_top.U1_ddr_dqs_io.bidi_dqs bidi_dqs ..\..\models\ecp2m\ddr_dqs_io.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\ddr_dqs_io.v
instance1 pll_120M ..\..\models\ecp2m\pll_120M.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\pll_120M.v
U1_RAM_DP RAM_DP ..\..\..\ram_dp\RAM_DP.v d:\ddr2_sdram\ram_dp\RAM_DP.v
pll_266M pll_266M ..\..\models\ecp2m\pll_266M.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\pll_266M.v
U1_ddr_sdram_mem_core ddr2 ..\..\..\ddr2_bb.v d:\ddr2_sdram\ddr2_bb.v
U1_ddr_sdram_mem_io_top.U1_ddr_data_io ddr_data_io ..\..\models\ecp2m\ddr_data_io.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\ddr_data_io.v
U1_ddr_sdram_mem_io_top.U1_ddr_data_io.bidi_cell bidi_cell ..\..\models\ecp2m\ddr_data_io.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\ddr_data_io.v
U1_ddr_sdram_mem_io_top.U1_ddr_dm_io ddr_dm_io ..\..\models\ecp2m\ddr_dm_io.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\ddr_dm_io.v
U1_ddr_sdram_mem_io_top.U1_ddr_dqs_io ddr_dqs_io ..\..\models\ecp2m\ddr_dqs_io.v d:\ddr2_sdram\ddr_p_eval\models\ecp2m\ddr_dqs_io.v