pll_120m.vm

DDR2 的控制器

//
// Written by Synplify
// Product Version "Version 8.8L2"
// Program "Synplify", Mapper "8.8.0, Build 018R"
// Fri Oct 12 15:30:02 2007
//
// Source file index table:
// Object locations will have the form <file>:<line>
// file 0 "noname"
// file 1 "\e:\isptools7_0\synpbase\lib\lucent\ecp2m.v "
// file 2 "\e:\isptools7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v "
// file 3 "\d:\ddr2_s~1\ddr_p_~1\ddr2\impl\ddr2_eval.h "
// file 4 "\d:\ddr2_s~1\ddr_p_~1\models\ecp2m\pll_120m.v "

`timescale 100 ps/100 ps
module pll_120M (
  CLK,
  CLKOP,
  CLKOK,
  LOCK
)
;
input CLK ;
output CLKOP ;
output CLKOK ;
output LOCK ;
wire CLK ;
wire CLKOP ;
wire CLKOK ;
wire LOCK ;
wire CLKOS ;
wire CLKINTFB ;
wire GND ;
wire VCC ;
wire CLK_c ;
wire CLKOP_c ;
wire CLKOK_c ;
wire LOCK_c ;
wire GND_Z ;
wire VCC_Z ;
  PUR PUR_INST (
	.PUR(VCC)
);
  GSR GSR_INST (
	.GSR(VCC)
);
  VHI VCC_0 (
	.Z(VCC)
);
  VLO GND_0 (
	.Z(GND)
);
// @4:12
  OB LOCK_pad (
	.I(LOCK_c),
	.O(LOCK)
);
// @4:11
  OB CLKOK_pad (
	.I(CLKOK_c),
	.O(CLKOK)
);
// @4:10
  OB CLKOP_pad (
	.I(CLKOP_c),
	.O(CLKOP)
);
// @4:9
  IB CLK_pad (
	.I(CLK),
	.O(CLK_c)
);
// @4:30
  EPLLD PLLDInst_0 (
	.CLKI(CLK_c),
	.CLKFB(CLKOP_c),
	.RST(GND),
	.RSTK(GND),
	.DPAMODE(GND),
	.DRPAI3(GND),
	.DRPAI2(GND),
	.DRPAI1(GND),
	.DRPAI0(GND),
	.DFPAI3(GND),
	.DFPAI2(GND),
	.DFPAI1(GND),
	.DFPAI0(GND),
	.CLKOP(CLKOP_c),
	.CLKOS(CLKOS),
	.CLKOK(CLKOK_c),
	.LOCK(LOCK_c),
	.CLKINTFB(CLKINTFB)
);
defparam PLLDInst_0.FIN = "80.000000";
defparam PLLDInst_0.CLKI_DIV = "2";
defparam PLLDInst_0.CLKFB_DIV = "3";
defparam PLLDInst_0.CLKOP_DIV = "8";
defparam PLLDInst_0.CLKOK_DIV = "2";
defparam PLLDInst_0.PHASEADJ = "0.0";
defparam PLLDInst_0.DUTY = "8";
defparam PLLDInst_0.PHASE_CNTL = "STATIC";
defparam PLLDInst_0.CLKOP_BYPASS = "DISABLED";
defparam PLLDInst_0.CLKOS_BYPASS = "DISABLED";
defparam PLLDInst_0.CLKOK_BYPASS = "DISABLED";
  assign GND_Z = 1'b0;
  assign VCC_Z = 1'b1;
endmodule /* pll_120M */