ddr2_eval.lct

DDR2 的控制器

[Device]
Family = ep5m00;
PartNumber = LFE2M35E-6F256CES;
Package = FPBGA256;
PartType = LFE2M35E;
Speed = -6;
Operating_condition = COM;
Status = Production;

[Revision]
Parent = ep5m00.lci;
DATE = 2002;
TIME = 0:00:00;
Source_Format = Schematic_Verilog_HDL;
Synthesis = Synplify;

[Ignore Assignments]

[Clear Assignments]

[Backannotate Assignments]

[Global Constraints]

[Location Assignments]
layer = OFF;

[Group Assignments]
layer = OFF;

[Resource Reservations]
layer = OFF;

[Fitter Report Format]

[Power]

[Source Constraint Option]

[Fast Bypass]

[OSM Bypass]

[Input Registers]

[Netlist/Delay Format]

[IO Types]
layer = OFF;

[Pullup]

[Slewrate]

[Region]

[Timing Constraints]

[HSI Attributes]

[Input Delay]

[global constraints list]

[Global Constraints Process Update]

[LOCATION ASSIGNMENTS LIST]

[RESOURCE RESERVATIONS LIST]

[Pin attributes list]

[Timing Analyzer]

[PLL Assignments]

[Explorer Results]

[Explorer User Settings]

[Explorer Run Settings]