ddr_sdram_mem_top.sdc

DDR2 的控制器

# Synplicity, Inc. constraint file
# C:\shared\PROJECTS\DDR2_400_p\synthesis\ec2\synplicity\config101\top\ddr_sdram_mem_top.sdc
# Written on Wed Oct 12 13:23:52 2005
# by Synplify for Lattice, Synplify for Lattice 8.2C Scope Editor

#
# Clocks
#
define_clock            -name {clk_in}  -freq 320.000 -clockgroup default_clkgroup
#
# Clock to Clock
#

#
# Inputs/Outputs
#
define_input_delay -disable      -default -improve 0.00 -route 0.00
define_output_delay -disable     -default -improve 0.00 -route 0.00
define_input_delay -disable      {addr[24:0]} -improve 0.00 -route 0.00
define_input_delay -disable      {burst_count[4:0]} -improve 0.00 -route 0.00
define_input_delay -disable      {burst_term} -improve 0.00 -route 0.00
define_input_delay -disable      {clk_in} -improve 0.00 -route 0.00
define_input_delay -disable      {cmd[3:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {cmd_rdy} -improve 0.00 -route 0.00
define_input_delay -disable      {cmd_valid} -improve 0.00 -route 0.00
define_input_delay -disable      {data_mask[7:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {data_rdy} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_addr[11:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_ba[1:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_cas_n} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_cke} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_clk} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_clk1} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_clk1_n} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_cs_n[3:0]} -improve 0.00 -route 0.00
define_input_delay -disable      {em_ddr_data[31:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_data[31:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_dm[3:0]} -improve 0.00 -route 0.00
define_input_delay -disable      {em_ddr_dqs[3:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_dqs[3:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_ras_n} -improve 0.00 -route 0.00
define_output_delay -disable     {em_ddr_we_n} -improve 0.00 -route 0.00
define_output_delay -disable     {init_done} -improve 0.00 -route 0.00
define_input_delay -disable      {init_start} -improve 0.00 -route 0.00
define_output_delay -disable     {read_data[63:0]} -improve 0.00 -route 0.00
define_output_delay -disable     {read_data_valid} -improve 0.00 -route 0.00
define_input_delay -disable      {rst_n} -improve 0.00 -route 0.00
define_input_delay -disable      {write_data[63:0]} -improve 0.00 -route 0.00

#
# Registers
#

#
# Multicycle Path
#

#
# False Path
#
define_false_path           -from {{p:rst_n}} 

#
# Path Delay
#

#
# Attributes
#

#
# I/O standards
#

#
# Other Constraints
#