pll_120m.tlg

来自「DDR2 的控制器」· TLG 代码 · 共 8 行

Selecting top level module pll_120M
@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":1276:7:1276:9|Synthesizing module VLO

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":311:7:311:11|Synthesizing module EPLLD

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\pll_120M.v":8:7:8:14|Synthesizing module pll_120M