ram_dp.lpc

DDR2 的控制器

[Device]
Family=latticeecp2m
PartType=LFE2M35E
PartName=LFE2M35E-6F256CES
SpeedGrade=-6
Package=FPBGA256
OperatingCondition=COM
Status=P

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=RAM_DP
CoreRevision=4.1
ModuleName=RAM_DP
SourceFormat=Schematic/Verilog HDL
ParameterFileVersion=1.0
Date=10/12/2007
Time=15:01:36

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=BusA(0 to 7)
Order=Big Endian [MSB:LSB]
IO=0
RAddress=8192
RData=32
WAddress=8192
WData=32
adPipeline=0
inPipeline=0
outPipeline=1
MOR=0
InData=Registered
AdControl=Registered
MemFile=
MemFormat=bin
Reset=Sync
GSR=Enabled
Pad=0
EnECC=0