ram_dp.tlg

来自「DDR2 的控制器」· TLG 代码 · 共 12 行

Selecting top level module RAM_DP
@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":1271:7:1271:9|Synthesizing module VHI

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":1577:7:1577:12|Synthesizing module DP16KB

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":1276:7:1276:9|Synthesizing module VLO

@N: CG364 :"D:\DDR2_S~1\ram_dp\RAM_DP.v":8:7:8:12|Synthesizing module RAM_DP

@W: CL168 :"D:\DDR2_S~1\ram_dp\RAM_DP.v":22:8:22:21|Pruning instance scuba_vhi_inst - not in use ...