pll_120m.cmd

DDR2 的控制器

STYFILENAME: ddr2_eval.sty
PROJECT: pll_120M
WORKING_PATH: "d:/ddr2_sdram/ddr_p_eval/ddr2/impl"
MODULE: pll_120M
VERILOG_FILE_LIST: "e:/ispTOOLS7_0/ispcpld/../cae_library/synthesis/verilog/ecp2m.v" ddr2_eval.h ../../models/ecp2m/pll_120M.v
OUTPUT_FILE_NAME: pll_120M
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -6
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0