ddr_sdram_mem_top.tlg

DDR2 的控制器

Selecting top level module ddr_sdram_mem_top
@N: CG364 :"D:\DDR2_S~1\ddr2_bb.v":15:7:15:10|Synthesizing module ddr2

@W: CG146 :"D:\DDR2_S~1\ddr2_bb.v":15:7:15:10|Creating black box for empty module ddr2

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_data_io.v":8:7:8:17|Synthesizing module ddr_data_io

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":722:7:722:15|Synthesizing module IDDRMFX1A

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":732:7:732:13|Synthesizing module ODDRMXA

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":179:7:179:8|Synthesizing module BB

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_data_io.v":71:7:71:15|Synthesizing module bidi_cell

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_dm_io.v":8:7:8:15|Synthesizing module ddr_dm_io

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_dqs_io.v":8:7:8:16|Synthesizing module ddr_dqs_io

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":727:7:727:12|Synthesizing module ODDRXC

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":747:7:747:13|Synthesizing module DQSBUFC

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_dqs_io.v":85:7:85:14|Synthesizing module bidi_dqs

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_dqs_io.v":127:11:127:24|No assignment to wire data_valid_lut

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":8:7:8:26|Synthesizing module ddr_sdram_mem_io_top

@W: CG133 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":107:39:107:49|No assignment to update_cntl
@W: CG133 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":108:39:108:48|No assignment to open_latch
@W: CG133 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":109:40:109:55|No assignment to latch_ctrl_count
@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":115:40:115:45|No assignment to wire ddr_dm

@W: CG133 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":116:40:116:48|No assignment to ddr_dm_d0
@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":118:40:118:53|No assignment to wire ddr_write_data

@W: CG133 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":119:40:119:56|No assignment to ddr_write_data_d0
@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":128:39:128:46|No assignment to wire pio_read

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":129:39:129:50|No assignment to wire read_command

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":151:39:151:45|No assignment to wire sec_clk

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":1276:7:1276:9|Synthesizing module VLO

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":331:7:331:13|Synthesizing module EHXPLLD

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\pll_266M.v":8:7:8:14|Synthesizing module pll_266M

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":742:7:742:12|Synthesizing module DQSDLL

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":800:7:800:9|Synthesizing module INV

@N: CG364 :"e:\ispTOOLS7_0\ispcpld\..\cae_library\synthesis\verilog\ecp2m.v":590:7:590:9|Synthesizing module GSR

@N: CG364 :"D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v":8:7:8:23|Synthesizing module ddr_sdram_mem_top

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v":167:36:167:46|No assignment to wire dqsxfer_clk

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v":168:36:168:44|No assignment to wire dqsin_clk

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v":178:36:178:48|No assignment to wire al_data_valid

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v":203:30:203:34|No assignment to wire CLKOS

@W: CG360 :"D:\DDR2_S~1\DDR_P_~1\ddr2\src\rtl\top\ecp2m\ddr_sdram_mem_top.v":216:47:216:54|No assignment to wire dqsdel_1

@W: CL159 :"D:\DDR2_S~1\DDR_P_~1\models\ecp2m\ddr_sdram_mem_io_top.v":66:39:66:43|Input rst_n is unused