pll_120m.vhm

DDR2 的控制器

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Fri Oct 12 15:30:02 2007
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Fri Oct 12 15:30:02 2007
--

-- No definition of black box work.EPLLD.verilog
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity pll_120M is
port(
  CLK :  in std_logic;
  CLKOP :  out std_logic;
  CLKOK :  out std_logic;
  LOCK :  out std_logic);
end pll_120M;

architecture beh of pll_120M is
  signal CLKOS : std_logic ;
  signal CLKINTFB : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal CLK_C : std_logic ;
  signal CLKOP_C : std_logic ;
  signal CLKOK_C : std_logic ;
  signal LOCK_C : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
  component EPLLD
    port(
      CLKI :  in std_logic;
      CLKFB :  in std_logic;
      RST :  in std_logic;
      RSTK :  in std_logic;
      DPAMODE :  in std_logic;
      DRPAI3 :  in std_logic;
      DRPAI2 :  in std_logic;
      DRPAI1 :  in std_logic;
      DRPAI0 :  in std_logic;
      DFPAI3 :  in std_logic;
      DFPAI2 :  in std_logic;
      DFPAI1 :  in std_logic;
      DFPAI0 :  in std_logic;
      CLKOP :  out std_logic;
      CLKOS :  out std_logic;
      CLKOK :  out std_logic;
      LOCK :  out std_logic;
      CLKINTFB :  out std_logic  );
  end component;
begin
  PUR_INST: PUR port map (
      PUR => VCC);
  GSR_INST: GSR port map (
      GSR => VCC);
  VCC_0: VHI port map (
      Z => VCC);
  GND_0: VLO port map (
      Z => GND);
  LOCK_PAD: OB port map (
      I => LOCK_C,
      O => LOCK);
  CLKOK_PAD: OB port map (
      I => CLKOK_C,
      O => CLKOK);
  CLKOP_PAD: OB port map (
      I => CLKOP_C,
      O => CLKOP);
  CLK_PAD: IB port map (
      I => CLK,
      O => CLK_C);
  PLLDINST_0: EPLLD port map (
      CLKI => CLK_C,
      CLKFB => CLKOP_C,
      RST => GND,
      RSTK => GND,
      DPAMODE => GND,
      DRPAI3 => GND,
      DRPAI2 => GND,
      DRPAI1 => GND,
      DRPAI0 => GND,
      DFPAI3 => GND,
      DFPAI2 => GND,
      DFPAI1 => GND,
      DFPAI0 => GND,
      CLKOP => CLKOP_C,
      CLKOS => CLKOS,
      CLKOK => CLKOK_C,
      LOCK => LOCK_C,
      CLKINTFB => CLKINTFB);
  NN_1 <= '0';
  NN_2 <= '1';
end beh;