pll.lpc

来自「DDR2 的控制器」· LPC 代码 · 共 56 行

[Device]
Family=latticeecp2m
PartType=LFE2M35E
PartName=LFE2M35E-5F256CES
SpeedGrade=-5
Package=FPBGA256
OperatingCondition=COM
Status=P

[IP]
VendorName=Lattice Semiconductor Corporation
CoreType=LPM
CoreStatus=Demo
CoreName=PLL
CoreRevision=3.5
ModuleName=pll
SourceFormat=Schematic/Verilog HDL
ParameterFileVersion=1.0
Date=10/12/2007
Time=11:29:04

[Parameters]
Verilog=1
VHDL=0
EDIF=1
Destination=Synplicity
Expression=None
Order=None
IO=0
Type=ehxpllb
mode=advanced
IFrq=80
OFrq=266.666667
KFrq=133.333333
U_OFrq=100
U_KFrq=50
OP_Tol=0.0
OK_Tol=0.0
Div=3
Mult=10
Post=8
SecD=2
fb_mode=CLKOP
PhaseDuty=Static
DelayControl=Static
PCDR=0
ClkOPBp=0
EnCLKOS=1
ClkOSBp=0
Phase=0.0
Duty=8
DPD=50% Duty
EnCLKOK=1
ClkOKBp=0
ClkRst=0