📄 pll_120m.edi
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(edif pll_120M
(edifVersion 2 0 0)
(edifLevel 0)
(keywordMap (keywordLevel 0))
(status
(written
(timeStamp 2007 10 12 15 30 2)
(author "Synplicity, Inc.")
(program "Synplify" (version "Version 8.8L2, mapper 8.8.0, Build 018R"))
)
)
(library LUCENT
(edifLevel 0)
(technology (numberDefinition ))
(cell OB (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell IB (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port I (direction INPUT))
(port O (direction OUTPUT))
)
)
)
(cell PUR (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port PUR (direction INPUT))
)
)
)
(cell GSR (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port GSR (direction INPUT))
)
)
)
(cell VHI (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port Z (direction OUTPUT))
)
)
)
(cell VLO (cellType GENERIC)
(view PRIM (viewType NETLIST)
(interface
(port Z (direction OUTPUT))
)
)
)
)
(library work
(edifLevel 0)
(technology (numberDefinition ))
(cell EPLLD (cellType GENERIC)
(view verilog (viewType NETLIST)
(interface
(port CLKI (direction INPUT))
(port CLKFB (direction INPUT))
(port RST (direction INPUT))
(port RSTK (direction INPUT))
(port DPAMODE (direction INPUT))
(port DRPAI3 (direction INPUT))
(port DRPAI2 (direction INPUT))
(port DRPAI1 (direction INPUT))
(port DRPAI0 (direction INPUT))
(port DFPAI3 (direction INPUT))
(port DFPAI2 (direction INPUT))
(port DFPAI1 (direction INPUT))
(port DFPAI0 (direction INPUT))
(port CLKOP (direction OUTPUT))
(port CLKOS (direction OUTPUT))
(port CLKOK (direction OUTPUT))
(port LOCK (direction OUTPUT))
(port CLKINTFB (direction OUTPUT))
)
(property CLKOK_BYPASS (string "DISABLED"))
(property CLKOS_BYPASS (string "DISABLED"))
(property CLKOP_BYPASS (string "DISABLED"))
(property PLLCAP (string "DISABLED"))
(property PHASE_CNTL (string "STATIC"))
(property DUTY (integer 4))
(property PHASEADJ (string "0.0"))
(property CLKOK_DIV (integer 1))
(property CLKOP_DIV (integer 1))
(property CLKFB_DIV (integer 1))
(property CLKI_DIV (integer 1))
(property FIN (string "100.0000"))
)
)
(cell pll_120M (cellType GENERIC)
(view verilog (viewType NETLIST)
(interface
(port CLK (direction INPUT)
)
(port CLKOP (direction OUTPUT))
(port CLKOK (direction OUTPUT))
(port LOCK (direction OUTPUT))
)
(contents
(instance PUR_INST (viewRef PRIM (cellRef PUR (libraryRef LUCENT)))
)
(instance GSR_INST (viewRef PRIM (cellRef GSR (libraryRef LUCENT)))
)
(instance VCC_0 (viewRef PRIM (cellRef VHI (libraryRef LUCENT))) )
(instance GND_0 (viewRef PRIM (cellRef VLO (libraryRef LUCENT))) )
(instance LOCK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance CLKOK_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance CLKOP_pad (viewRef PRIM (cellRef OB (libraryRef LUCENT))) )
(instance CLK_pad (viewRef PRIM (cellRef IB (libraryRef LUCENT))) )
(instance PLLDInst_0 (viewRef verilog (cellRef EPLLD))
(property CLKOK_BYPASS (string "DISABLED"))
(property FREQUENCY_PIN_CLKOK (string "60.000000"))
(property CLKOK_DIV (string "2"))
(property CLKOS_BYPASS (string "DISABLED"))
(property FREQUENCY_PIN_CLKOP (string "120.000000"))
(property CLKOP_BYPASS (string "DISABLED"))
(property PHASE_CNTL (string "STATIC"))
(property FDEL (string "0"))
(property DUTY (string "8"))
(property PHASEADJ (string "0.0"))
(property FREQUENCY_PIN_CLKI (string "80.000000"))
(property CLKOP_DIV (string "8"))
(property CLKFB_DIV (string "3"))
(property CLKI_DIV (string "2"))
(property FIN (string "80.000000"))
)
(net CLKOS (joined
(portRef CLKOS (instanceRef PLLDInst_0))
))
(net CLKINTFB (joined
(portRef CLKINTFB (instanceRef PLLDInst_0))
))
(net GND (joined
(portRef Z (instanceRef GND_0))
(portRef DFPAI0 (instanceRef PLLDInst_0))
(portRef DFPAI1 (instanceRef PLLDInst_0))
(portRef DFPAI2 (instanceRef PLLDInst_0))
(portRef DFPAI3 (instanceRef PLLDInst_0))
(portRef DRPAI0 (instanceRef PLLDInst_0))
(portRef DRPAI1 (instanceRef PLLDInst_0))
(portRef DRPAI2 (instanceRef PLLDInst_0))
(portRef DRPAI3 (instanceRef PLLDInst_0))
(portRef DPAMODE (instanceRef PLLDInst_0))
(portRef RSTK (instanceRef PLLDInst_0))
(portRef RST (instanceRef PLLDInst_0))
))
(net VCC (joined
(portRef Z (instanceRef VCC_0))
(portRef GSR (instanceRef GSR_INST))
(portRef PUR (instanceRef PUR_INST))
))
(net CLK_c (joined
(portRef O (instanceRef CLK_pad))
(portRef CLKI (instanceRef PLLDInst_0))
))
(net CLK (joined
(portRef CLK)
(portRef I (instanceRef CLK_pad))
))
(net CLKOP_c (joined
(portRef CLKOP (instanceRef PLLDInst_0))
(portRef CLKFB (instanceRef PLLDInst_0))
(portRef I (instanceRef CLKOP_pad))
))
(net CLKOP (joined
(portRef O (instanceRef CLKOP_pad))
(portRef CLKOP)
))
(net CLKOK_c (joined
(portRef CLKOK (instanceRef PLLDInst_0))
(portRef I (instanceRef CLKOK_pad))
))
(net CLKOK (joined
(portRef O (instanceRef CLKOK_pad))
(portRef CLKOK)
))
(net LOCK_c (joined
(portRef LOCK (instanceRef PLLDInst_0))
(portRef I (instanceRef LOCK_pad))
))
(net LOCK (joined
(portRef O (instanceRef LOCK_pad))
(portRef LOCK)
))
)
)
)
)
(design pll_120M (cellRef pll_120M (libraryRef work))
(property PART (string "lfe2m35e-6") ))
)
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