ddr2_top.cmd

DDR2 的控制器

STYFILENAME: ddr2_eval.sty
PROJECT: ddr_sdram_mem_top
WORKING_PATH: "D:/DDR2_sdram/ddr_p_eval/ddr2/impl/syn"
MODULE: ddr_sdram_mem_top
VERILOG_FILE_LIST: "E:/ispTOOLS7_0/ispcpld/tcltk/lib/ipwidgets/ispipbuilder/../../../../../cae_library/synthesis/verilog/ecp2m.v" "D:/DDR2_sdram/ddr2_bb.v" "D:/DDR2_sdram/ddr_p_eval/models/ecp2m/ddr_data_io.v" "D:/DDR2_sdram/ddr_p_eval/models/ecp2m/ddr_dm_io.v" "D:/DDR2_sdram/ddr_p_eval/models/ecp2m/ddr_dqs_io.v" "D:/DDR2_sdram/ddr_p_eval/models/ecp2m/ddr_sdram_mem_io_top.v" "D:/DDR2_sdram/ddr_p_eval/models/ecp2m/kbar_clk_pll.v" "D:/DDR2_sdram/ddr_p_eval/models/ecp2m/pmi_def.v" "D:/DDR2_sdram/ddr_p_eval/ddr2/src/rtl/top/ecp2m/ddr_sdram_mem_top.v"
OUTPUT_FILE_NAME: ddr_sdram_mem_top
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -6
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0