📄 ram_dp.vhm
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signal RAM_DP_0_11_4_DOB6 : std_logic ;
signal RAM_DP_0_11_4_DOB7 : std_logic ;
signal RAM_DP_0_11_4_DOB8 : std_logic ;
signal RAM_DP_0_11_4_DOB9 : std_logic ;
signal RAM_DP_0_11_4_DOB10 : std_logic ;
signal RAM_DP_0_11_4_DOB11 : std_logic ;
signal RAM_DP_0_11_4_DOB12 : std_logic ;
signal RAM_DP_0_11_4_DOB13 : std_logic ;
signal RAM_DP_0_11_4_DOB14 : std_logic ;
signal RAM_DP_0_11_4_DOB15 : std_logic ;
signal RAM_DP_0_11_4_DOB16 : std_logic ;
signal RAM_DP_0_11_4_DOB17 : std_logic ;
signal RAM_DP_0_12_3_DOA0 : std_logic ;
signal RAM_DP_0_12_3_DOA1 : std_logic ;
signal RAM_DP_0_12_3_DOA2 : std_logic ;
signal RAM_DP_0_12_3_DOA3 : std_logic ;
signal RAM_DP_0_12_3_DOA4 : std_logic ;
signal RAM_DP_0_12_3_DOA5 : std_logic ;
signal RAM_DP_0_12_3_DOA6 : std_logic ;
signal RAM_DP_0_12_3_DOA7 : std_logic ;
signal RAM_DP_0_12_3_DOA8 : std_logic ;
signal RAM_DP_0_12_3_DOA9 : std_logic ;
signal RAM_DP_0_12_3_DOA10 : std_logic ;
signal RAM_DP_0_12_3_DOA11 : std_logic ;
signal RAM_DP_0_12_3_DOA12 : std_logic ;
signal RAM_DP_0_12_3_DOA13 : std_logic ;
signal RAM_DP_0_12_3_DOA14 : std_logic ;
signal RAM_DP_0_12_3_DOA15 : std_logic ;
signal RAM_DP_0_12_3_DOA16 : std_logic ;
signal RAM_DP_0_12_3_DOA17 : std_logic ;
signal RAM_DP_0_12_3_DOB2 : std_logic ;
signal RAM_DP_0_12_3_DOB3 : std_logic ;
signal RAM_DP_0_12_3_DOB4 : std_logic ;
signal RAM_DP_0_12_3_DOB5 : std_logic ;
signal RAM_DP_0_12_3_DOB6 : std_logic ;
signal RAM_DP_0_12_3_DOB7 : std_logic ;
signal RAM_DP_0_12_3_DOB8 : std_logic ;
signal RAM_DP_0_12_3_DOB9 : std_logic ;
signal RAM_DP_0_12_3_DOB10 : std_logic ;
signal RAM_DP_0_12_3_DOB11 : std_logic ;
signal RAM_DP_0_12_3_DOB12 : std_logic ;
signal RAM_DP_0_12_3_DOB13 : std_logic ;
signal RAM_DP_0_12_3_DOB14 : std_logic ;
signal RAM_DP_0_12_3_DOB15 : std_logic ;
signal RAM_DP_0_12_3_DOB16 : std_logic ;
signal RAM_DP_0_12_3_DOB17 : std_logic ;
signal RAM_DP_0_13_2_DOA0 : std_logic ;
signal RAM_DP_0_13_2_DOA1 : std_logic ;
signal RAM_DP_0_13_2_DOA2 : std_logic ;
signal RAM_DP_0_13_2_DOA3 : std_logic ;
signal RAM_DP_0_13_2_DOA4 : std_logic ;
signal RAM_DP_0_13_2_DOA5 : std_logic ;
signal RAM_DP_0_13_2_DOA6 : std_logic ;
signal RAM_DP_0_13_2_DOA7 : std_logic ;
signal RAM_DP_0_13_2_DOA8 : std_logic ;
signal RAM_DP_0_13_2_DOA9 : std_logic ;
signal RAM_DP_0_13_2_DOA10 : std_logic ;
signal RAM_DP_0_13_2_DOA11 : std_logic ;
signal RAM_DP_0_13_2_DOA12 : std_logic ;
signal RAM_DP_0_13_2_DOA13 : std_logic ;
signal RAM_DP_0_13_2_DOA14 : std_logic ;
signal RAM_DP_0_13_2_DOA15 : std_logic ;
signal RAM_DP_0_13_2_DOA16 : std_logic ;
signal RAM_DP_0_13_2_DOA17 : std_logic ;
signal RAM_DP_0_13_2_DOB2 : std_logic ;
signal RAM_DP_0_13_2_DOB3 : std_logic ;
signal RAM_DP_0_13_2_DOB4 : std_logic ;
signal RAM_DP_0_13_2_DOB5 : std_logic ;
signal RAM_DP_0_13_2_DOB6 : std_logic ;
signal RAM_DP_0_13_2_DOB7 : std_logic ;
signal RAM_DP_0_13_2_DOB8 : std_logic ;
signal RAM_DP_0_13_2_DOB9 : std_logic ;
signal RAM_DP_0_13_2_DOB10 : std_logic ;
signal RAM_DP_0_13_2_DOB11 : std_logic ;
signal RAM_DP_0_13_2_DOB12 : std_logic ;
signal RAM_DP_0_13_2_DOB13 : std_logic ;
signal RAM_DP_0_13_2_DOB14 : std_logic ;
signal RAM_DP_0_13_2_DOB15 : std_logic ;
signal RAM_DP_0_13_2_DOB16 : std_logic ;
signal RAM_DP_0_13_2_DOB17 : std_logic ;
signal RAM_DP_0_14_1_DOA0 : std_logic ;
signal RAM_DP_0_14_1_DOA1 : std_logic ;
signal RAM_DP_0_14_1_DOA2 : std_logic ;
signal RAM_DP_0_14_1_DOA3 : std_logic ;
signal RAM_DP_0_14_1_DOA4 : std_logic ;
signal RAM_DP_0_14_1_DOA5 : std_logic ;
signal RAM_DP_0_14_1_DOA6 : std_logic ;
signal RAM_DP_0_14_1_DOA7 : std_logic ;
signal RAM_DP_0_14_1_DOA8 : std_logic ;
signal RAM_DP_0_14_1_DOA9 : std_logic ;
signal RAM_DP_0_14_1_DOA10 : std_logic ;
signal RAM_DP_0_14_1_DOA11 : std_logic ;
signal RAM_DP_0_14_1_DOA12 : std_logic ;
signal RAM_DP_0_14_1_DOA13 : std_logic ;
signal RAM_DP_0_14_1_DOA14 : std_logic ;
signal RAM_DP_0_14_1_DOA15 : std_logic ;
signal RAM_DP_0_14_1_DOA16 : std_logic ;
signal RAM_DP_0_14_1_DOA17 : std_logic ;
signal RAM_DP_0_14_1_DOB2 : std_logic ;
signal RAM_DP_0_14_1_DOB3 : std_logic ;
signal RAM_DP_0_14_1_DOB4 : std_logic ;
signal RAM_DP_0_14_1_DOB5 : std_logic ;
signal RAM_DP_0_14_1_DOB6 : std_logic ;
signal RAM_DP_0_14_1_DOB7 : std_logic ;
signal RAM_DP_0_14_1_DOB8 : std_logic ;
signal RAM_DP_0_14_1_DOB9 : std_logic ;
signal RAM_DP_0_14_1_DOB10 : std_logic ;
signal RAM_DP_0_14_1_DOB11 : std_logic ;
signal RAM_DP_0_14_1_DOB12 : std_logic ;
signal RAM_DP_0_14_1_DOB13 : std_logic ;
signal RAM_DP_0_14_1_DOB14 : std_logic ;
signal RAM_DP_0_14_1_DOB15 : std_logic ;
signal RAM_DP_0_14_1_DOB16 : std_logic ;
signal RAM_DP_0_14_1_DOB17 : std_logic ;
signal RAM_DP_0_15_0_DOA0 : std_logic ;
signal RAM_DP_0_15_0_DOA1 : std_logic ;
signal RAM_DP_0_15_0_DOA2 : std_logic ;
signal RAM_DP_0_15_0_DOA3 : std_logic ;
signal RAM_DP_0_15_0_DOA4 : std_logic ;
signal RAM_DP_0_15_0_DOA5 : std_logic ;
signal RAM_DP_0_15_0_DOA6 : std_logic ;
signal RAM_DP_0_15_0_DOA7 : std_logic ;
signal RAM_DP_0_15_0_DOA8 : std_logic ;
signal RAM_DP_0_15_0_DOA9 : std_logic ;
signal RAM_DP_0_15_0_DOA10 : std_logic ;
signal RAM_DP_0_15_0_DOA11 : std_logic ;
signal RAM_DP_0_15_0_DOA12 : std_logic ;
signal RAM_DP_0_15_0_DOA13 : std_logic ;
signal RAM_DP_0_15_0_DOA14 : std_logic ;
signal RAM_DP_0_15_0_DOA15 : std_logic ;
signal RAM_DP_0_15_0_DOA16 : std_logic ;
signal RAM_DP_0_15_0_DOA17 : std_logic ;
signal RAM_DP_0_15_0_DOB2 : std_logic ;
signal RAM_DP_0_15_0_DOB3 : std_logic ;
signal RAM_DP_0_15_0_DOB4 : std_logic ;
signal RAM_DP_0_15_0_DOB5 : std_logic ;
signal RAM_DP_0_15_0_DOB6 : std_logic ;
signal RAM_DP_0_15_0_DOB7 : std_logic ;
signal RAM_DP_0_15_0_DOB8 : std_logic ;
signal RAM_DP_0_15_0_DOB9 : std_logic ;
signal RAM_DP_0_15_0_DOB10 : std_logic ;
signal RAM_DP_0_15_0_DOB11 : std_logic ;
signal RAM_DP_0_15_0_DOB12 : std_logic ;
signal RAM_DP_0_15_0_DOB13 : std_logic ;
signal RAM_DP_0_15_0_DOB14 : std_logic ;
signal RAM_DP_0_15_0_DOB15 : std_logic ;
signal RAM_DP_0_15_0_DOB16 : std_logic ;
signal RAM_DP_0_15_0_DOB17 : std_logic ;
signal GND : std_logic ;
signal VCC : std_logic ;
signal RDCLOCK_C : std_logic ;
signal RDCLOCKEN_C : std_logic ;
signal RESET_C : std_logic ;
signal WRCLOCK_C : std_logic ;
signal WRCLOCKEN_C : std_logic ;
signal WE_C : std_logic ;
signal NN_1 : std_logic ;
signal NN_2 : std_logic ;
begin
PUR_INST: PUR port map (
PUR => VCC);
GSR_INST: GSR port map (
GSR => VCC);
VCC_0: VHI port map (
Z => VCC);
GND_0: VLO port map (
Z => GND);
\Q_PAD[31]\: OB port map (
I => Q_C(31),
O => Q(31));
\Q_PAD[30]\: OB port map (
I => Q_C(30),
O => Q(30));
\Q_PAD[29]\: OB port map (
I => Q_C(29),
O => Q(29));
\Q_PAD[28]\: OB port map (
I => Q_C(28),
O => Q(28));
\Q_PAD[27]\: OB port map (
I => Q_C(27),
O => Q(27));
\Q_PAD[26]\: OB port map (
I => Q_C(26),
O => Q(26));
\Q_PAD[25]\: OB port map (
I => Q_C(25),
O => Q(25));
\Q_PAD[24]\: OB port map (
I => Q_C(24),
O => Q(24));
\Q_PAD[23]\: OB port map (
I => Q_C(23),
O => Q(23));
\Q_PAD[22]\: OB port map (
I => Q_C(22),
O => Q(22));
\Q_PAD[21]\: OB port map (
I => Q_C(21),
O => Q(21));
\Q_PAD[20]\: OB port map (
I => Q_C(20),
O => Q(20));
\Q_PAD[19]\: OB port map (
I => Q_C(19),
O => Q(19));
\Q_PAD[18]\: OB port map (
I => Q_C(18),
O => Q(18));
\Q_PAD[17]\: OB port map (
I => Q_C(17),
O => Q(17));
\Q_PAD[16]\: OB port map (
I => Q_C(16),
O => Q(16));
\Q_PAD[15]\: OB port map (
I => Q_C(15),
O => Q(15));
\Q_PAD[14]\: OB port map (
I => Q_C(14),
O => Q(14));
\Q_PAD[13]\: OB port map (
I => Q_C(13),
O => Q(13));
\Q_PAD[12]\: OB port map (
I => Q_C(12),
O => Q(12));
\Q_PAD[11]\: OB port map (
I => Q_C(11),
O => Q(11));
\Q_PAD[10]\: OB port map (
I => Q_C(10),
O => Q(10));
\Q_PAD[9]\: OB port map (
I => Q_C(9),
O => Q(9));
\Q_PAD[8]\: OB port map (
I => Q_C(8),
O => Q(8));
\Q_PAD[7]\: OB port map (
I => Q_C(7),
O => Q(7));
\Q_PAD[6]\: OB port map (
I => Q_C(6),
O => Q(6));
\Q_PAD[5]\: OB port map (
I => Q_C(5),
O => Q(5));
\Q_PAD[4]\: OB port map (
I => Q_C(4),
O => Q(4));
\Q_PAD[3]\: OB port map (
I => Q_C(3),
O => Q(3));
\Q_PAD[2]\: OB port map (
I => Q_C(2),
O => Q(2));
\Q_PAD[1]\: OB port map (
I => Q_C(1),
O => Q(1));
\Q_PAD[0]\: OB port map (
I => Q_C(0),
O => Q(0));
WE_PAD: IB port map (
I => WE,
O => WE_C);
WRCLOCKEN_PAD: IB port map (
I => WrClockEn,
O => WRCLOCKEN_C);
WRCLOCK_PAD: IB port map (
I => WrClock,
O => WRCLOCK_C);
RESET_PAD: IB port map (
I => Reset,
O => RESET_C);
RDCLOCKEN_PAD: IB port map (
I => RdClockEn,
O => RDCLOCKEN_C);
RDCLOCK_PAD: IB port map (
I => RdClock,
O => RDCLOCK_C);
\DATA_PAD[31]\: IB port map (
I => Data(31),
O => DATA_C(31));
\DATA_PAD[30]\: IB port map (
I => Data(30),
O => DATA_C(30));
\DATA_PAD[29]\: IB port map (
I => Data(29),
O => DATA_C(29));
\DATA_PAD[28]\: IB port map (
I => Data(28),
O => DATA_C(28));
\DATA_PAD[27]\: IB port map (
I => Data(27),
O => DATA_C(27));
\DATA_PAD[26]\: IB port map (
I => Data(26),
O => DATA_C(26));
\DATA_PAD[25]\: IB port map (
I => Data(25),
O => DATA_C(25));
\DATA_PAD[24]\: IB port map (
I => Data(24),
O => DATA_C(24));
\DATA_PAD[23]\: IB port map (
I => Data(23),
O => DATA_C(23));
\DATA_PAD[22]\: IB port map (
I => Data(22),
O => DATA_C(22));
\DATA_PAD[21]\: IB port map (
I => Data(21),
O => DATA_C(21));
\DATA_PAD[20]\: IB port map (
I => Data(20),
O => DATA_C(20));
\DATA_PAD[19]\: IB port map (
I => Data(19),
O => DATA_C(19));
\DATA_PAD[18]\: IB port map (
I => Data(18),
O => DATA_C(18));
\DATA_PAD[17]\: IB port map (
I => Data(17),
O => DATA_C(17));
\DATA_PAD[16]\: IB port map (
I => Data(16),
O => DATA_C(16));
\DATA_PAD[15]\: IB port map (
I => Data(15),
O => DATA_C(15));
\DATA_PAD[14]\: IB port map (
I => Data(14),
O => DATA_C(14));
\DATA_PAD[13]\: IB port map (
I => Data(13),
O => DATA_C(13));
\DATA_PAD[12]\: IB port map (
I => Data(12),
O => DATA_C(12));
\DATA_PAD[11]\: IB port map (
I => Data(11),
O => DATA_C(11));
\DATA_PAD[10]\: IB port map (
I => Data(10),
O => DATA_C(10));
\DATA_PAD[9]\: IB port map (
I => Data(9),
O => DATA_C(9));
\DATA_PAD[8]\: IB port map (
I => Data(8),
O => DATA_C(8));
\DATA_PAD[7]\: IB port map (
I => Data(7),
O => DATA_C(7));
\DATA_PAD[6]\: IB port map (
I => Data(6),
O => DATA_C(6));
\DATA_PAD[5]\: IB port map (
I => Data(5),
O => DATA_C(5));
\DATA_PAD[4]\: IB port map (
I => Data(4),
O => DATA_C(4));
\DATA_PAD[3]\: IB port map (
I => Data(3),
O => DATA_C(3));
\DATA_PAD[2]\: IB port map (
I => Data(2),
O => DATA_C(2));
\DATA_PAD[1]\: IB port map (
I => Data(1),
O => DATA_C(1));
\DATA_PAD[0]\: IB port map (
I => Data(0),
O => DATA_C(0));
\RDADDRESS_PAD[12]\: IB port map (
I => RdAddress(12),
O => RDADDRESS_C(12));
\RDADDRESS_PAD[11]\: IB port map (
I => RdAddress(11),
O => RDADDRESS_C(11));
\RDADDRESS_PAD[10]\: IB port map (
I => RdAddress(10),
O => RDADDRESS_C(10));
\RDADDRESS_PAD[9]\: IB port map (
I => RdAddress(9),
O => RDADDRESS_C(9));
\RDADDRESS_PAD[8]\: IB port map (
I => RdAddress(8),
O => RDADDRESS_C(8));
\RDADDRESS_PAD[7]\: IB port map (
I => RdAddress(7),
O => RDADDRESS_C(7));
\RDADDRESS_PAD[6]\: IB port map (
I => RdAddress(6),
O => RDADDRESS_C(6));
\RDADDRESS_PAD[5]\: IB port map (
I => RdAddress(5),
O => RDADDRESS_C(5));
\RDADDRESS_PAD[4]\: IB port map (
I => RdAddress(4),
O => RDADDRESS_C(4));
\RDADDRESS_PAD[3]\: IB port map (
I => RdAddress(3),
O => RDADDRESS_C(3));
\RDADDRESS_PAD[2]\: IB port map (
I => RdAddress(2),
O => RDADDRESS_C(2));
\RDADDRESS_PAD[1]\: IB port map (
I => RdAddress(1),
O => RDADDRESS_C(1));
\RDADDRESS_PAD[0]\: IB port map (
I => RdAddress(0),
O => RDADDRESS_C(0));
\WRADDRESS_PAD[12]\: IB port map (
I => WrAddress(12),
O => WRADDRESS_C(12));
\WRADDRESS_PAD[11]\: IB port map (
I => WrAddress(11),
O => WRADDRESS_C(11));
\WRADDRESS_PAD[10]\: IB port map (
I => WrAddress(10),
O => WRADDRESS_C(10));
\WRADDRESS_PAD[9]\: IB port map (
I => WrAddress(9),
O => WRADDRESS_C(9));
\WRADDRESS_PAD[8]\: IB port map (
I => WrAddress(8),
O => WRADDRESS_C(8));
\WRADDRESS_PAD[7]\: IB port map (
I => WrAddress(7),
O => WRADDRESS_C(7));
\WRADDRESS_PAD[6]\: IB port map (
I => WrAddress(6),
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