ram_dp.vhm

DDR2 的控制器

--
-- Written by Synplicity
-- Product Version "Version 8.8L2"
-- Program "Synplify", Mapper "8.8.0, Build 018R"
-- Fri Oct 12 15:22:57 2007
--

--
-- Written by Synplify version 8.8.0, Build 018R
-- Fri Oct 12 15:22:57 2007
--

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library ecp2;
use ecp2.components.all;

entity RAM_DP is
port(
  WrAddress : in std_logic_vector(12 downto 0);
  RdAddress : in std_logic_vector(12 downto 0);
  Data : in std_logic_vector(31 downto 0);
  RdClock :  in std_logic;
  RdClockEn :  in std_logic;
  Reset :  in std_logic;
  WrClock :  in std_logic;
  WrClockEn :  in std_logic;
  WE :  in std_logic;
  Q : out std_logic_vector(31 downto 0));
end RAM_DP;

architecture beh of RAM_DP is
  signal WRADDRESS_C : std_logic_vector(12 downto 0);
  signal RDADDRESS_C : std_logic_vector(12 downto 0);
  signal DATA_C : std_logic_vector(31 downto 0);
  signal Q_C : std_logic_vector(31 downto 0);
  signal RAM_DP_0_0_15_DOA0 : std_logic ;
  signal RAM_DP_0_0_15_DOA1 : std_logic ;
  signal RAM_DP_0_0_15_DOA2 : std_logic ;
  signal RAM_DP_0_0_15_DOA3 : std_logic ;
  signal RAM_DP_0_0_15_DOA4 : std_logic ;
  signal RAM_DP_0_0_15_DOA5 : std_logic ;
  signal RAM_DP_0_0_15_DOA6 : std_logic ;
  signal RAM_DP_0_0_15_DOA7 : std_logic ;
  signal RAM_DP_0_0_15_DOA8 : std_logic ;
  signal RAM_DP_0_0_15_DOA9 : std_logic ;
  signal RAM_DP_0_0_15_DOA10 : std_logic ;
  signal RAM_DP_0_0_15_DOA11 : std_logic ;
  signal RAM_DP_0_0_15_DOA12 : std_logic ;
  signal RAM_DP_0_0_15_DOA13 : std_logic ;
  signal RAM_DP_0_0_15_DOA14 : std_logic ;
  signal RAM_DP_0_0_15_DOA15 : std_logic ;
  signal RAM_DP_0_0_15_DOA16 : std_logic ;
  signal RAM_DP_0_0_15_DOA17 : std_logic ;
  signal RAM_DP_0_0_15_DOB2 : std_logic ;
  signal RAM_DP_0_0_15_DOB3 : std_logic ;
  signal RAM_DP_0_0_15_DOB4 : std_logic ;
  signal RAM_DP_0_0_15_DOB5 : std_logic ;
  signal RAM_DP_0_0_15_DOB6 : std_logic ;
  signal RAM_DP_0_0_15_DOB7 : std_logic ;
  signal RAM_DP_0_0_15_DOB8 : std_logic ;
  signal RAM_DP_0_0_15_DOB9 : std_logic ;
  signal RAM_DP_0_0_15_DOB10 : std_logic ;
  signal RAM_DP_0_0_15_DOB11 : std_logic ;
  signal RAM_DP_0_0_15_DOB12 : std_logic ;
  signal RAM_DP_0_0_15_DOB13 : std_logic ;
  signal RAM_DP_0_0_15_DOB14 : std_logic ;
  signal RAM_DP_0_0_15_DOB15 : std_logic ;
  signal RAM_DP_0_0_15_DOB16 : std_logic ;
  signal RAM_DP_0_0_15_DOB17 : std_logic ;
  signal RAM_DP_0_1_14_DOA0 : std_logic ;
  signal RAM_DP_0_1_14_DOA1 : std_logic ;
  signal RAM_DP_0_1_14_DOA2 : std_logic ;
  signal RAM_DP_0_1_14_DOA3 : std_logic ;
  signal RAM_DP_0_1_14_DOA4 : std_logic ;
  signal RAM_DP_0_1_14_DOA5 : std_logic ;
  signal RAM_DP_0_1_14_DOA6 : std_logic ;
  signal RAM_DP_0_1_14_DOA7 : std_logic ;
  signal RAM_DP_0_1_14_DOA8 : std_logic ;
  signal RAM_DP_0_1_14_DOA9 : std_logic ;
  signal RAM_DP_0_1_14_DOA10 : std_logic ;
  signal RAM_DP_0_1_14_DOA11 : std_logic ;
  signal RAM_DP_0_1_14_DOA12 : std_logic ;
  signal RAM_DP_0_1_14_DOA13 : std_logic ;
  signal RAM_DP_0_1_14_DOA14 : std_logic ;
  signal RAM_DP_0_1_14_DOA15 : std_logic ;
  signal RAM_DP_0_1_14_DOA16 : std_logic ;
  signal RAM_DP_0_1_14_DOA17 : std_logic ;
  signal RAM_DP_0_1_14_DOB2 : std_logic ;
  signal RAM_DP_0_1_14_DOB3 : std_logic ;
  signal RAM_DP_0_1_14_DOB4 : std_logic ;
  signal RAM_DP_0_1_14_DOB5 : std_logic ;
  signal RAM_DP_0_1_14_DOB6 : std_logic ;
  signal RAM_DP_0_1_14_DOB7 : std_logic ;
  signal RAM_DP_0_1_14_DOB8 : std_logic ;
  signal RAM_DP_0_1_14_DOB9 : std_logic ;
  signal RAM_DP_0_1_14_DOB10 : std_logic ;
  signal RAM_DP_0_1_14_DOB11 : std_logic ;
  signal RAM_DP_0_1_14_DOB12 : std_logic ;
  signal RAM_DP_0_1_14_DOB13 : std_logic ;
  signal RAM_DP_0_1_14_DOB14 : std_logic ;
  signal RAM_DP_0_1_14_DOB15 : std_logic ;
  signal RAM_DP_0_1_14_DOB16 : std_logic ;
  signal RAM_DP_0_1_14_DOB17 : std_logic ;
  signal RAM_DP_0_2_13_DOA0 : std_logic ;
  signal RAM_DP_0_2_13_DOA1 : std_logic ;
  signal RAM_DP_0_2_13_DOA2 : std_logic ;
  signal RAM_DP_0_2_13_DOA3 : std_logic ;
  signal RAM_DP_0_2_13_DOA4 : std_logic ;
  signal RAM_DP_0_2_13_DOA5 : std_logic ;
  signal RAM_DP_0_2_13_DOA6 : std_logic ;
  signal RAM_DP_0_2_13_DOA7 : std_logic ;
  signal RAM_DP_0_2_13_DOA8 : std_logic ;
  signal RAM_DP_0_2_13_DOA9 : std_logic ;
  signal RAM_DP_0_2_13_DOA10 : std_logic ;
  signal RAM_DP_0_2_13_DOA11 : std_logic ;
  signal RAM_DP_0_2_13_DOA12 : std_logic ;
  signal RAM_DP_0_2_13_DOA13 : std_logic ;
  signal RAM_DP_0_2_13_DOA14 : std_logic ;
  signal RAM_DP_0_2_13_DOA15 : std_logic ;
  signal RAM_DP_0_2_13_DOA16 : std_logic ;
  signal RAM_DP_0_2_13_DOA17 : std_logic ;
  signal RAM_DP_0_2_13_DOB2 : std_logic ;
  signal RAM_DP_0_2_13_DOB3 : std_logic ;
  signal RAM_DP_0_2_13_DOB4 : std_logic ;
  signal RAM_DP_0_2_13_DOB5 : std_logic ;
  signal RAM_DP_0_2_13_DOB6 : std_logic ;
  signal RAM_DP_0_2_13_DOB7 : std_logic ;
  signal RAM_DP_0_2_13_DOB8 : std_logic ;
  signal RAM_DP_0_2_13_DOB9 : std_logic ;
  signal RAM_DP_0_2_13_DOB10 : std_logic ;
  signal RAM_DP_0_2_13_DOB11 : std_logic ;
  signal RAM_DP_0_2_13_DOB12 : std_logic ;
  signal RAM_DP_0_2_13_DOB13 : std_logic ;
  signal RAM_DP_0_2_13_DOB14 : std_logic ;
  signal RAM_DP_0_2_13_DOB15 : std_logic ;
  signal RAM_DP_0_2_13_DOB16 : std_logic ;
  signal RAM_DP_0_2_13_DOB17 : std_logic ;
  signal RAM_DP_0_3_12_DOA0 : std_logic ;
  signal RAM_DP_0_3_12_DOA1 : std_logic ;
  signal RAM_DP_0_3_12_DOA2 : std_logic ;
  signal RAM_DP_0_3_12_DOA3 : std_logic ;
  signal RAM_DP_0_3_12_DOA4 : std_logic ;
  signal RAM_DP_0_3_12_DOA5 : std_logic ;
  signal RAM_DP_0_3_12_DOA6 : std_logic ;
  signal RAM_DP_0_3_12_DOA7 : std_logic ;
  signal RAM_DP_0_3_12_DOA8 : std_logic ;
  signal RAM_DP_0_3_12_DOA9 : std_logic ;
  signal RAM_DP_0_3_12_DOA10 : std_logic ;
  signal RAM_DP_0_3_12_DOA11 : std_logic ;
  signal RAM_DP_0_3_12_DOA12 : std_logic ;
  signal RAM_DP_0_3_12_DOA13 : std_logic ;
  signal RAM_DP_0_3_12_DOA14 : std_logic ;
  signal RAM_DP_0_3_12_DOA15 : std_logic ;
  signal RAM_DP_0_3_12_DOA16 : std_logic ;
  signal RAM_DP_0_3_12_DOA17 : std_logic ;
  signal RAM_DP_0_3_12_DOB2 : std_logic ;
  signal RAM_DP_0_3_12_DOB3 : std_logic ;
  signal RAM_DP_0_3_12_DOB4 : std_logic ;
  signal RAM_DP_0_3_12_DOB5 : std_logic ;
  signal RAM_DP_0_3_12_DOB6 : std_logic ;
  signal RAM_DP_0_3_12_DOB7 : std_logic ;
  signal RAM_DP_0_3_12_DOB8 : std_logic ;
  signal RAM_DP_0_3_12_DOB9 : std_logic ;
  signal RAM_DP_0_3_12_DOB10 : std_logic ;
  signal RAM_DP_0_3_12_DOB11 : std_logic ;
  signal RAM_DP_0_3_12_DOB12 : std_logic ;
  signal RAM_DP_0_3_12_DOB13 : std_logic ;
  signal RAM_DP_0_3_12_DOB14 : std_logic ;
  signal RAM_DP_0_3_12_DOB15 : std_logic ;
  signal RAM_DP_0_3_12_DOB16 : std_logic ;
  signal RAM_DP_0_3_12_DOB17 : std_logic ;
  signal RAM_DP_0_4_11_DOA0 : std_logic ;
  signal RAM_DP_0_4_11_DOA1 : std_logic ;
  signal RAM_DP_0_4_11_DOA2 : std_logic ;
  signal RAM_DP_0_4_11_DOA3 : std_logic ;
  signal RAM_DP_0_4_11_DOA4 : std_logic ;
  signal RAM_DP_0_4_11_DOA5 : std_logic ;
  signal RAM_DP_0_4_11_DOA6 : std_logic ;
  signal RAM_DP_0_4_11_DOA7 : std_logic ;
  signal RAM_DP_0_4_11_DOA8 : std_logic ;
  signal RAM_DP_0_4_11_DOA9 : std_logic ;
  signal RAM_DP_0_4_11_DOA10 : std_logic ;
  signal RAM_DP_0_4_11_DOA11 : std_logic ;
  signal RAM_DP_0_4_11_DOA12 : std_logic ;
  signal RAM_DP_0_4_11_DOA13 : std_logic ;
  signal RAM_DP_0_4_11_DOA14 : std_logic ;
  signal RAM_DP_0_4_11_DOA15 : std_logic ;
  signal RAM_DP_0_4_11_DOA16 : std_logic ;
  signal RAM_DP_0_4_11_DOA17 : std_logic ;
  signal RAM_DP_0_4_11_DOB2 : std_logic ;
  signal RAM_DP_0_4_11_DOB3 : std_logic ;
  signal RAM_DP_0_4_11_DOB4 : std_logic ;
  signal RAM_DP_0_4_11_DOB5 : std_logic ;
  signal RAM_DP_0_4_11_DOB6 : std_logic ;
  signal RAM_DP_0_4_11_DOB7 : std_logic ;
  signal RAM_DP_0_4_11_DOB8 : std_logic ;
  signal RAM_DP_0_4_11_DOB9 : std_logic ;
  signal RAM_DP_0_4_11_DOB10 : std_logic ;
  signal RAM_DP_0_4_11_DOB11 : std_logic ;
  signal RAM_DP_0_4_11_DOB12 : std_logic ;
  signal RAM_DP_0_4_11_DOB13 : std_logic ;
  signal RAM_DP_0_4_11_DOB14 : std_logic ;
  signal RAM_DP_0_4_11_DOB15 : std_logic ;
  signal RAM_DP_0_4_11_DOB16 : std_logic ;
  signal RAM_DP_0_4_11_DOB17 : std_logic ;
  signal RAM_DP_0_5_10_DOA0 : std_logic ;
  signal RAM_DP_0_5_10_DOA1 : std_logic ;
  signal RAM_DP_0_5_10_DOA2 : std_logic ;
  signal RAM_DP_0_5_10_DOA3 : std_logic ;
  signal RAM_DP_0_5_10_DOA4 : std_logic ;
  signal RAM_DP_0_5_10_DOA5 : std_logic ;
  signal RAM_DP_0_5_10_DOA6 : std_logic ;
  signal RAM_DP_0_5_10_DOA7 : std_logic ;
  signal RAM_DP_0_5_10_DOA8 : std_logic ;
  signal RAM_DP_0_5_10_DOA9 : std_logic ;
  signal RAM_DP_0_5_10_DOA10 : std_logic ;
  signal RAM_DP_0_5_10_DOA11 : std_logic ;
  signal RAM_DP_0_5_10_DOA12 : std_logic ;
  signal RAM_DP_0_5_10_DOA13 : std_logic ;
  signal RAM_DP_0_5_10_DOA14 : std_logic ;
  signal RAM_DP_0_5_10_DOA15 : std_logic ;
  signal RAM_DP_0_5_10_DOA16 : std_logic ;
  signal RAM_DP_0_5_10_DOA17 : std_logic ;
  signal RAM_DP_0_5_10_DOB2 : std_logic ;
  signal RAM_DP_0_5_10_DOB3 : std_logic ;
  signal RAM_DP_0_5_10_DOB4 : std_logic ;
  signal RAM_DP_0_5_10_DOB5 : std_logic ;
  signal RAM_DP_0_5_10_DOB6 : std_logic ;
  signal RAM_DP_0_5_10_DOB7 : std_logic ;
  signal RAM_DP_0_5_10_DOB8 : std_logic ;
  signal RAM_DP_0_5_10_DOB9 : std_logic ;
  signal RAM_DP_0_5_10_DOB10 : std_logic ;
  signal RAM_DP_0_5_10_DOB11 : std_logic ;
  signal RAM_DP_0_5_10_DOB12 : std_logic ;
  signal RAM_DP_0_5_10_DOB13 : std_logic ;
  signal RAM_DP_0_5_10_DOB14 : std_logic ;
  signal RAM_DP_0_5_10_DOB15 : std_logic ;
  signal RAM_DP_0_5_10_DOB16 : std_logic ;
  signal RAM_DP_0_5_10_DOB17 : std_logic ;
  signal RAM_DP_0_6_9_DOA0 : std_logic ;
  signal RAM_DP_0_6_9_DOA1 : std_logic ;
  signal RAM_DP_0_6_9_DOA2 : std_logic ;
  signal RAM_DP_0_6_9_DOA3 : std_logic ;
  signal RAM_DP_0_6_9_DOA4 : std_logic ;
  signal RAM_DP_0_6_9_DOA5 : std_logic ;
  signal RAM_DP_0_6_9_DOA6 : std_logic ;
  signal RAM_DP_0_6_9_DOA7 : std_logic ;
  signal RAM_DP_0_6_9_DOA8 : std_logic ;
  signal RAM_DP_0_6_9_DOA9 : std_logic ;
  signal RAM_DP_0_6_9_DOA10 : std_logic ;
  signal RAM_DP_0_6_9_DOA11 : std_logic ;
  signal RAM_DP_0_6_9_DOA12 : std_logic ;
  signal RAM_DP_0_6_9_DOA13 : std_logic ;
  signal RAM_DP_0_6_9_DOA14 : std_logic ;
  signal RAM_DP_0_6_9_DOA15 : std_logic ;
  signal RAM_DP_0_6_9_DOA16 : std_logic ;
  signal RAM_DP_0_6_9_DOA17 : std_logic ;
  signal RAM_DP_0_6_9_DOB2 : std_logic ;
  signal RAM_DP_0_6_9_DOB3 : std_logic ;
  signal RAM_DP_0_6_9_DOB4 : std_logic ;
  signal RAM_DP_0_6_9_DOB5 : std_logic ;
  signal RAM_DP_0_6_9_DOB6 : std_logic ;
  signal RAM_DP_0_6_9_DOB7 : std_logic ;
  signal RAM_DP_0_6_9_DOB8 : std_logic ;
  signal RAM_DP_0_6_9_DOB9 : std_logic ;
  signal RAM_DP_0_6_9_DOB10 : std_logic ;
  signal RAM_DP_0_6_9_DOB11 : std_logic ;
  signal RAM_DP_0_6_9_DOB12 : std_logic ;
  signal RAM_DP_0_6_9_DOB13 : std_logic ;
  signal RAM_DP_0_6_9_DOB14 : std_logic ;
  signal RAM_DP_0_6_9_DOB15 : std_logic ;
  signal RAM_DP_0_6_9_DOB16 : std_logic ;
  signal RAM_DP_0_6_9_DOB17 : std_logic ;
  signal RAM_DP_0_7_8_DOA0 : std_logic ;
  signal RAM_DP_0_7_8_DOA1 : std_logic ;
  signal RAM_DP_0_7_8_DOA2 : std_logic ;
  signal RAM_DP_0_7_8_DOA3 : std_logic ;
  signal RAM_DP_0_7_8_DOA4 : std_logic ;
  signal RAM_DP_0_7_8_DOA5 : std_logic ;
  signal RAM_DP_0_7_8_DOA6 : std_logic ;
  signal RAM_DP_0_7_8_DOA7 : std_logic ;
  signal RAM_DP_0_7_8_DOA8 : std_logic ;
  signal RAM_DP_0_7_8_DOA9 : std_logic ;
  signal RAM_DP_0_7_8_DOA10 : std_logic ;
  signal RAM_DP_0_7_8_DOA11 : std_logic ;
  signal RAM_DP_0_7_8_DOA12 : std_logic ;
  signal RAM_DP_0_7_8_DOA13 : std_logic ;
  signal RAM_DP_0_7_8_DOA14 : std_logic ;
  signal RAM_DP_0_7_8_DOA15 : std_logic ;
  signal RAM_DP_0_7_8_DOA16 : std_logic ;
  signal RAM_DP_0_7_8_DOA17 : std_logic ;
  signal RAM_DP_0_7_8_DOB2 : std_logic ;
  signal RAM_DP_0_7_8_DOB3 : std_logic ;
  signal RAM_DP_0_7_8_DOB4 : std_logic ;
  signal RAM_DP_0_7_8_DOB5 : std_logic ;
  signal RAM_DP_0_7_8_DOB6 : std_logic ;
  signal RAM_DP_0_7_8_DOB7 : std_logic ;
  signal RAM_DP_0_7_8_DOB8 : std_logic ;
  signal RAM_DP_0_7_8_DOB9 : std_logic ;
  signal RAM_DP_0_7_8_DOB10 : std_logic ;
  signal RAM_DP_0_7_8_DOB11 : std_logic ;
  signal RAM_DP_0_7_8_DOB12 : std_logic ;
  signal RAM_DP_0_7_8_DOB13 : std_logic ;
  signal RAM_DP_0_7_8_DOB14 : std_logic ;
  signal RAM_DP_0_7_8_DOB15 : std_logic ;
  signal RAM_DP_0_7_8_DOB16 : std_logic ;
  signal RAM_DP_0_7_8_DOB17 : std_logic ;
  signal RAM_DP_0_8_7_DOA0 : std_logic ;
  signal RAM_DP_0_8_7_DOA1 : std_logic ;
  signal RAM_DP_0_8_7_DOA2 : std_logic ;
  signal RAM_DP_0_8_7_DOA3 : std_logic ;
  signal RAM_DP_0_8_7_DOA4 : std_logic ;
  signal RAM_DP_0_8_7_DOA5 : std_logic ;
  signal RAM_DP_0_8_7_DOA6 : std_logic ;
  signal RAM_DP_0_8_7_DOA7 : std_logic ;
  signal RAM_DP_0_8_7_DOA8 : std_logic ;
  signal RAM_DP_0_8_7_DOA9 : std_logic ;
  signal RAM_DP_0_8_7_DOA10 : std_logic ;
  signal RAM_DP_0_8_7_DOA11 : std_logic ;
  signal RAM_DP_0_8_7_DOA12 : std_logic ;
  signal RAM_DP_0_8_7_DOA13 : std_logic ;
  signal RAM_DP_0_8_7_DOA14 : std_logic ;
  signal RAM_DP_0_8_7_DOA15 : std_logic ;
  signal RAM_DP_0_8_7_DOA16 : std_logic ;
  signal RAM_DP_0_8_7_DOA17 : std_logic ;
  signal RAM_DP_0_8_7_DOB2 : std_logic ;
  signal RAM_DP_0_8_7_DOB3 : std_logic ;
  signal RAM_DP_0_8_7_DOB4 : std_logic ;
  signal RAM_DP_0_8_7_DOB5 : std_logic ;
  signal RAM_DP_0_8_7_DOB6 : std_logic ;
  signal RAM_DP_0_8_7_DOB7 : std_logic ;
  signal RAM_DP_0_8_7_DOB8 : std_logic ;
  signal RAM_DP_0_8_7_DOB9 : std_logic ;
  signal RAM_DP_0_8_7_DOB10 : std_logic ;
  signal RAM_DP_0_8_7_DOB11 : std_logic ;
  signal RAM_DP_0_8_7_DOB12 : std_logic ;
  signal RAM_DP_0_8_7_DOB13 : std_logic ;
  signal RAM_DP_0_8_7_DOB14 : std_logic ;
  signal RAM_DP_0_8_7_DOB15 : std_logic ;
  signal RAM_DP_0_8_7_DOB16 : std_logic ;
  signal RAM_DP_0_8_7_DOB17 : std_logic ;
  signal RAM_DP_0_9_6_DOA0 : std_logic ;
  signal RAM_DP_0_9_6_DOA1 : std_logic ;
  signal RAM_DP_0_9_6_DOA2 : std_logic ;
  signal RAM_DP_0_9_6_DOA3 : std_logic ;
  signal RAM_DP_0_9_6_DOA4 : std_logic ;
  signal RAM_DP_0_9_6_DOA5 : std_logic ;
  signal RAM_DP_0_9_6_DOA6 : std_logic ;
  signal RAM_DP_0_9_6_DOA7 : std_logic ;
  signal RAM_DP_0_9_6_DOA8 : std_logic ;
  signal RAM_DP_0_9_6_DOA9 : std_logic ;
  signal RAM_DP_0_9_6_DOA10 : std_logic ;
  signal RAM_DP_0_9_6_DOA11 : std_logic ;
  signal RAM_DP_0_9_6_DOA12 : std_logic ;
  signal RAM_DP_0_9_6_DOA13 : std_logic ;
  signal RAM_DP_0_9_6_DOA14 : std_logic ;
  signal RAM_DP_0_9_6_DOA15 : std_logic ;
  signal RAM_DP_0_9_6_DOA16 : std_logic ;
  signal RAM_DP_0_9_6_DOA17 : std_logic ;
  signal RAM_DP_0_9_6_DOB2 : std_logic ;
  signal RAM_DP_0_9_6_DOB3 : std_logic ;
  signal RAM_DP_0_9_6_DOB4 : std_logic ;
  signal RAM_DP_0_9_6_DOB5 : std_logic ;
  signal RAM_DP_0_9_6_DOB6 : std_logic ;
  signal RAM_DP_0_9_6_DOB7 : std_logic ;
  signal RAM_DP_0_9_6_DOB8 : std_logic ;
  signal RAM_DP_0_9_6_DOB9 : std_logic ;
  signal RAM_DP_0_9_6_DOB10 : std_logic ;
  signal RAM_DP_0_9_6_DOB11 : std_logic ;
  signal RAM_DP_0_9_6_DOB12 : std_logic ;
  signal RAM_DP_0_9_6_DOB13 : std_logic ;
  signal RAM_DP_0_9_6_DOB14 : std_logic ;
  signal RAM_DP_0_9_6_DOB15 : std_logic ;
  signal RAM_DP_0_9_6_DOB16 : std_logic ;
  signal RAM_DP_0_9_6_DOB17 : std_logic ;
  signal RAM_DP_0_10_5_DOA0 : std_logic ;
  signal RAM_DP_0_10_5_DOA1 : std_logic ;
  signal RAM_DP_0_10_5_DOA2 : std_logic ;
  signal RAM_DP_0_10_5_DOA3 : std_logic ;
  signal RAM_DP_0_10_5_DOA4 : std_logic ;
  signal RAM_DP_0_10_5_DOA5 : std_logic ;
  signal RAM_DP_0_10_5_DOA6 : std_logic ;
  signal RAM_DP_0_10_5_DOA7 : std_logic ;
  signal RAM_DP_0_10_5_DOA8 : std_logic ;
  signal RAM_DP_0_10_5_DOA9 : std_logic ;
  signal RAM_DP_0_10_5_DOA10 : std_logic ;
  signal RAM_DP_0_10_5_DOA11 : std_logic ;
  signal RAM_DP_0_10_5_DOA12 : std_logic ;
  signal RAM_DP_0_10_5_DOA13 : std_logic ;
  signal RAM_DP_0_10_5_DOA14 : std_logic ;
  signal RAM_DP_0_10_5_DOA15 : std_logic ;
  signal RAM_DP_0_10_5_DOA16 : std_logic ;
  signal RAM_DP_0_10_5_DOA17 : std_logic ;
  signal RAM_DP_0_10_5_DOB2 : std_logic ;
  signal RAM_DP_0_10_5_DOB3 : std_logic ;
  signal RAM_DP_0_10_5_DOB4 : std_logic ;
  signal RAM_DP_0_10_5_DOB5 : std_logic ;
  signal RAM_DP_0_10_5_DOB6 : std_logic ;
  signal RAM_DP_0_10_5_DOB7 : std_logic ;
  signal RAM_DP_0_10_5_DOB8 : std_logic ;
  signal RAM_DP_0_10_5_DOB9 : std_logic ;
  signal RAM_DP_0_10_5_DOB10 : std_logic ;
  signal RAM_DP_0_10_5_DOB11 : std_logic ;
  signal RAM_DP_0_10_5_DOB12 : std_logic ;
  signal RAM_DP_0_10_5_DOB13 : std_logic ;
  signal RAM_DP_0_10_5_DOB14 : std_logic ;
  signal RAM_DP_0_10_5_DOB15 : std_logic ;
  signal RAM_DP_0_10_5_DOB16 : std_logic ;
  signal RAM_DP_0_10_5_DOB17 : std_logic ;
  signal RAM_DP_0_11_4_DOA0 : std_logic ;
  signal RAM_DP_0_11_4_DOA1 : std_logic ;
  signal RAM_DP_0_11_4_DOA2 : std_logic ;
  signal RAM_DP_0_11_4_DOA3 : std_logic ;
  signal RAM_DP_0_11_4_DOA4 : std_logic ;
  signal RAM_DP_0_11_4_DOA5 : std_logic ;
  signal RAM_DP_0_11_4_DOA6 : std_logic ;
  signal RAM_DP_0_11_4_DOA7 : std_logic ;
  signal RAM_DP_0_11_4_DOA8 : std_logic ;
  signal RAM_DP_0_11_4_DOA9 : std_logic ;
  signal RAM_DP_0_11_4_DOA10 : std_logic ;
  signal RAM_DP_0_11_4_DOA11 : std_logic ;
  signal RAM_DP_0_11_4_DOA12 : std_logic ;
  signal RAM_DP_0_11_4_DOA13 : std_logic ;
  signal RAM_DP_0_11_4_DOA14 : std_logic ;
  signal RAM_DP_0_11_4_DOA15 : std_logic ;
  signal RAM_DP_0_11_4_DOA16 : std_logic ;
  signal RAM_DP_0_11_4_DOA17 : std_logic ;
  signal RAM_DP_0_11_4_DOB2 : std_logic ;
  signal RAM_DP_0_11_4_DOB3 : std_logic ;
  signal RAM_DP_0_11_4_DOB4 : std_logic ;
  signal RAM_DP_0_11_4_DOB5 : std_logic ;