ddr2_eval.tcl

DDR2 的控制器

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# Commands to make the Process: 
# Synplify Synthesize Verilog File
if [catch {open ddr2_eval.rvp w} rspFile] {
	puts stderr "Cannot create response file ddr2_eval.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=ddr2_eval.sty
PROJECT=ddr2_eval
ENTRY=Schematic/Verilog HDL
WORKING_PATH=$proj_dir
MODULE=ddr_sdram_mem_top
TOP_FILE=../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
EDF_FILE_LIST=../../models/ecp2m/ddr_dqs_io.v ../../../ddr2_bb.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../models/ecp2m/pll_266M.v ../../models/ecp2m/ddr_data_io.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v ../../models/ecp2m/kbar_clk_pll.v ../../models/ecp2m/ddr_dm_io.v DDR2_eval.h
VHDL_FILE_LIST=
VERILOG_FILE_LIST=ddr2_eval.h ../../models/ecp2m/pll_266M.v ../../models/ecp2m/ddr_dqs_io.v ../../models/ecp2m/ddr_dm_io.v ../../models/ecp2m/ddr_data_io.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../../ddr2_bb.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
DEVICEPART=LFE2M35E-6F256CES
"
	close $rspFile
}
if [catch {open ddr_sdram_mem_top.cmd w} rspFile] {
	puts stderr "Cannot create response file ddr_sdram_mem_top.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: ddr2_eval.sty
PROJECT: ddr_sdram_mem_top
WORKING_PATH: \"$proj_dir\"
MODULE: ddr_sdram_mem_top
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" ddr2_eval.h ../../models/ecp2m/pll_266M.v ../../models/ecp2m/ddr_dqs_io.v ../../models/ecp2m/ddr_dm_io.v ../../models/ecp2m/ddr_data_io.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../../ddr2_bb.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
OUTPUT_FILE_NAME: ddr_sdram_mem_top
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -6
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e ddr_sdram_mem_top -target LATTICE-ecp2m -part LFE2M35E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../ddr2_bb.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_sdram_mem_io_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../ram_dp/RAM_DP.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/pll_266M.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_dm_io.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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# Commands to make the Process: 
# Synplify Synthesize Verilog File
if [catch {open ddr2_eval.rvp w} rspFile] {
	puts stderr "Cannot create response file ddr2_eval.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=ddr2_eval.sty
PROJECT=ddr2_eval
ENTRY=Schematic/Verilog HDL
WORKING_PATH=$proj_dir
MODULE=ddr_sdram_mem_top
TOP_FILE=../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
EDF_FILE_LIST=../../models/ecp2m/ddr_dqs_io.v ../../../ddr2_bb.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../../ram_dp/RAM_DP.v ../../models/ecp2m/pll_266M.v ../../models/ecp2m/ddr_data_io.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v ../../models/ecp2m/ddr_dm_io.v DDR2_eval.h
VHDL_FILE_LIST=
VERILOG_FILE_LIST=ddr2_eval.h ../../../ram_dp/RAM_DP.v
DEVICEPART=LFE2M35E-6F256CES
"
	close $rspFile
}
if [catch {open RAM_DP.cmd w} rspFile] {
	puts stderr "Cannot create response file RAM_DP.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: ddr2_eval.sty
PROJECT: RAM_DP
WORKING_PATH: \"$proj_dir\"
MODULE: RAM_DP
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" ddr2_eval.h ../../../ram_dp/RAM_DP.v
OUTPUT_FILE_NAME: RAM_DP
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -6
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e RAM_DP -target LATTICE-ecp2m -part LFE2M35E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/pll_120M.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 10/12/07 15:29:57 ##########

# Commands to make the Process: 
# Synplify Synthesize Verilog File
if [catch {open ddr2_eval.rvp w} rspFile] {
	puts stderr "Cannot create response file ddr2_eval.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=ddr2_eval.sty
PROJECT=ddr2_eval
ENTRY=Schematic/Verilog HDL
WORKING_PATH=$proj_dir
MODULE=ddr_sdram_mem_top
TOP_FILE=../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
EDF_FILE_LIST=../../models/ecp2m/ddr_dqs_io.v ../../models/ecp2m/pll_120M.v ../../../ddr2_bb.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../../ram_dp/RAM_DP.v ../../models/ecp2m/pll_266M.v ../../models/ecp2m/ddr_data_io.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v ../../models/ecp2m/ddr_dm_io.v DDR2_eval.h
VHDL_FILE_LIST=
VERILOG_FILE_LIST=ddr2_eval.h ../../models/ecp2m/pll_120M.v
DEVICEPART=LFE2M35E-6F256CES
"
	close $rspFile
}
if [catch {open pll_120M.cmd w} rspFile] {
	puts stderr "Cannot create response file pll_120M.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: ddr2_eval.sty
PROJECT: pll_120M
WORKING_PATH: \"$proj_dir\"
MODULE: pll_120M
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" ddr2_eval.h ../../models/ecp2m/pll_120M.v
OUTPUT_FILE_NAME: pll_120M
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -6
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e pll_120M -target LATTICE-ecp2m -part LFE2M35E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 10/12/07 15:44:32 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 10/12/07 15:46:26 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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