ddr2_eval.tcl

DDR2 的控制器

########## Tcl recorder starts at 10/12/07 13:59:49 ##########

set version "7.0"
set proj_dir "D:/DDR2_sdram/ddr_p_eval/DDR2/impl"
cd $proj_dir

# Get directory paths
set pver $version
regsub -all {\.} $pver {_} pver
set lscfile "lsc_"
append lscfile $pver ".ini"
set lsvini_dir [lindex [array get env LSC_INI_PATH] 1]
set lsvini_path [file join $lsvini_dir $lscfile]
if {[catch {set fid [open $lsvini_path]} msg]} {
	 puts "File Open Error: $lsvini_path"
	 return false
} else {set data [read $fid]; close $fid }
foreach line [split $data '\n'] { 
	set lline [string tolower $line]
	set lline [string trim $lline]
	if {[string compare $lline "\[paths\]"] == 0} { set path 1; continue}
	if {$path && [regexp {^\[} $lline]} {set path 0; break}
	if {$path && [regexp {^bin} $lline]} {set cpld_bin $line; continue}
	if {$path && [regexp {^fpgapath} $lline]} {set fpga_dir $line; continue}
	if {$path && [regexp {^fpgabinpath} $lline]} {set fpga_bin $line}}

set cpld_bin [string range $cpld_bin [expr [string first "=" $cpld_bin]+1] end]
regsub -all "\"" $cpld_bin "" cpld_bin
set cpld_bin [file join $cpld_bin]
set install_dir [string range $cpld_bin 0 [expr [string first "ispcpld" $cpld_bin]-2]]
regsub -all "\"" $install_dir "" install_dir
set install_dir [file join $install_dir]
set fpga_dir [string range $fpga_dir [expr [string first "=" $fpga_dir]+1] end]
regsub -all "\"" $fpga_dir "" fpga_dir
set fpga_dir [file join $fpga_dir]
set fpga_bin [string range $fpga_bin [expr [string first "=" $fpga_bin]+1] end]
regsub -all "\"" $fpga_bin "" fpga_bin
set fpga_bin [file join $fpga_bin]

if {[string match "*$fpga_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$fpga_bin;$env(PATH)" }

if {[string match "*$cpld_bin;*" $env(PATH)] == 0 } {
   set env(PATH) "$cpld_bin;$env(PATH)" }

lappend auto_path [file join $install_dir "ispcpld" "tcltk" "lib" "ispwidget" "runproc"]
package require runcmd

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_dqs_io.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../ddr2_bb.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_sdram_mem_io_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_data_io.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/kbar_clk_pll.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_dm_io.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 10/12/07 13:59:49 ###########


########## Tcl recorder starts at 10/12/07 14:33:48 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../pll_266.667/pll.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 10/12/07 14:33:48 ###########


########## Tcl recorder starts at 10/12/07 14:39:37 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../pll_266.667/pll.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 10/12/07 14:39:37 ###########


########## Tcl recorder starts at 10/12/07 14:41:44 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../../ddr2_bb.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_sdram_mem_io_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/kbar_clk_pll.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/ddr_dm_io.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 10/12/07 14:41:44 ###########


########## Tcl recorder starts at 10/12/07 14:41:45 ##########

# Commands to make the Process: 
# Synplify Synthesize Verilog File
if [catch {open ddr2_eval.rvp w} rspFile] {
	puts stderr "Cannot create response file ddr2_eval.rvp: $rspFile"
} else {
	puts $rspFile "STYFILENAME=ddr2_eval.sty
PROJECT=ddr2_eval
ENTRY=Schematic/Verilog HDL
WORKING_PATH=$proj_dir
MODULE=ddr_sdram_mem_top
TOP_FILE=../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
EDF_FILE_LIST=../../models/ecp2m/ddr_dqs_io.v ../../../ddr2_bb.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../models/ecp2m/ddr_data_io.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v ../../models/ecp2m/kbar_clk_pll.v ../../models/ecp2m/ddr_dm_io.v DDR2_eval.h
VHDL_FILE_LIST=
VERILOG_FILE_LIST=ddr2_eval.h ../../models/ecp2m/kbar_clk_pll.v ../../models/ecp2m/ddr_dqs_io.v ../../models/ecp2m/ddr_dm_io.v ../../models/ecp2m/ddr_data_io.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../../ddr2_bb.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
DEVICEPART=LFE2M35E-6F256CES
"
	close $rspFile
}
if [catch {open ddr_sdram_mem_top.cmd w} rspFile] {
	puts stderr "Cannot create response file ddr_sdram_mem_top.cmd: $rspFile"
} else {
	puts $rspFile "STYFILENAME: ddr2_eval.sty
PROJECT: ddr_sdram_mem_top
WORKING_PATH: \"$proj_dir\"
MODULE: ddr_sdram_mem_top
VERILOG_FILE_LIST: \"$install_dir/ispcpld/../cae_library/synthesis/verilog/ecp2m.v\" ddr2_eval.h ../../models/ecp2m/kbar_clk_pll.v ../../models/ecp2m/ddr_dqs_io.v ../../models/ecp2m/ddr_dm_io.v ../../models/ecp2m/ddr_data_io.v ../../models/ecp2m/ddr_sdram_mem_io_top.v ../../../ddr2_bb.v ../src/rtl/top/ecp2m/ddr_sdram_mem_top.v
OUTPUT_FILE_NAME: ddr_sdram_mem_top
SUFFIX_NAME: edi
WRITE_PRF: false
Vlog_std_v2001: true
FREQUENCY:  200
FANOUT_LIMIT:  100
DISABLE_IO_INSERTION: false
FORCE_GSR: auto
SPEED_GRADE: -6
SYMBOLIC_FSM_COMPILER: true
NUM_CRITICAL_PATHS:  3
AUTO_CONSTRAIN_IO: true
NUM_STARTEND_POINTS:  0
"
	close $rspFile
}
if [runCmd "\"$cpld_bin/Synpwrap\" -rem -e ddr_sdram_mem_top -target LATTICE-ecp2m -part LFE2M35E"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

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########## Tcl recorder starts at 10/12/07 14:45:03 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../../models/ecp2m/pll_266M.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 10/12/07 14:45:03 ###########


########## Tcl recorder starts at 10/12/07 14:46:20 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}

########## Tcl recorder end at 10/12/07 14:46:20 ###########


########## Tcl recorder starts at 10/12/07 14:49:43 ##########

# Commands to make the Process: 
# Hierarchy
if [runCmd "\"$cpld_bin/vlog2jhd\" \"../src/rtl/top/ecp2m/ddr_sdram_mem_top.v\" -p \"$install_dir/ispcpld/../cae_library/synthesis/verilog\" -pf ecp2m.v -noglib -predefine ddr2_eval.h -setting ddr2_eval.sty"] {
	return
} else {
	vwait done
	if [checkResult $done] {
		return
	}
}